CMOS Dual-Mode Imager Noise and Linearity
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Solution Overview
Problem
Current-mode imagers suffer from higher noise levels and poorer image quality due to their inability to provide improved image quality while facilitating focal-plane image processing.
Innovation Solution
A dual-mode imager capable of both voltage-mode and current-mode readout, with a unified layout and access scheme, using optimized readout transistors and correlated double sampling units to reduce noise and enhance linearity, allowing for simultaneous readout of both modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If current-mode readout is used to facilitate focal-plane image processing, then image processing capability is improved, but noise level increases and image quality deteriorates
Solution Approach 1:
The patent implements dynamic mode switching capability that allows the imager to operate in either voltage-mode or current-mode readout based on application requirements. The mode switch enables the system to adapt between different operating states, selecting voltage-mode when high image quality is prioritized and current-mode when focal-plane processing capability is needed, thus resolving the contradiction between processing capability and image quality.
Solution Approach 2:
The patent segments the readout functionality into distinct voltage-mode and current-mode pathways with separate optimized circuits for each mode. By providing dedicated readout circuits for each mode rather than a single unified circuit, the system can optimize each pathway independently - the voltage-mode pathway for high quality imaging and the current-mode pathway for focal-plane processing, eliminating the compromise required by a single-mode design.
2Reliability
If voltage-mode readout is used, then image quality is improved, but focal-plane image processing capability is limited
Solution Approach 1:
The patent creates a universal imager architecture that incorporates both voltage-mode and current-mode readout capabilities within a single device. The dual-mode design with shared pixel array and separate readout circuits enables the system to perform both high-quality imaging (voltage-mode) and focal-plane processing (current-mode), making the device multi-functional and adaptable to different application requirements without needing separate specialized imagers.
3Adaptability or versatility
If current-mode readout is used, then focal-plane processing is facilitated, but linearity deteriorates
Solution Approach 1:
The patent employs dynamic biasing conditions for the current-mode readout transistor, allowing it to operate in different regions (linear region or velocity saturation region) depending on the application. This dynamic operation enables the system to achieve both good linearity (when operating in linear region) and focal-plane processing capability (when operating in velocity saturation region with optimized transistor sizing), resolving the contradiction between linearity and processing capability.
4Reliability
If mode-specific readout transistors are used for each mode, then performance in each mode is optimized, but device complexity increases
Solution Approach 1:
The patent segments the readout functionality into separate optimized circuits for voltage-mode and current-mode operation. By providing dedicated readout transistors and circuits for each mode rather than attempting to use a single circuit for both modes, the system achieves optimal performance in each mode while keeping the overall architecture manageable through clear functional separation.
Data Source
AI summary
A CMOS image sensor that is capable of both voltage- and current-mode operations selects the mode based on the position of mode switches. Each pixel on the imager has a single transistor acting as either source follower for voltage readout, or transconductor for current readout. The two modes share the same readout lines, but have their own correlated double sampling (CDS) units for noise suppression. A current-mode readout technique using a velocity-saturated short-channel transistor may be used to achieve high linearity. An image array may be formed as a mixture of 3 types of pixels with identical photodiodes and access switches. The readout transistors are optimally sized for their designated mode of operation. Alternatively, two readout transistors are provided per pixel, each individually optimized for the desired mode of operation.