Temperature-Compensated CMOS Driving Circuit With Edge Detection
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Solution Overview
Problem
Conventional LSI driving circuits with CMOS inverters face issues such as varying delay times due to temperature changes, excessive power consumption, cross-talk problems, and insufficient driving capacity, which complicate design and increase costs, especially in portable equipment.
Innovation Solution
A driving circuit that includes an edge detector or level detector to generate signals with pulse widths corresponding to ambient temperature, and transistors controlled by these signals to adjust the output node, thereby stabilizing delay times and increasing driving capacity while minimizing through current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CMOS inverters are used in the driving circuit, then the circuit can operate, but the delay time varies with ambient temperature causing irregularities in operation timings
Solution Approach 1:
The patent uses delay detection circuits to measure the actual delay time of the driving circuit and feeds this information back to control circuits. The control circuits then adjust the driving signals to compensate for temperature-induced delay variations, maintaining consistent operation timings across different temperature conditions
Solution Approach 2:
The patent dynamically changes operating parameters (such as driving signal characteristics) based on detected delay time variations. By adjusting parameters like signal amplitude or pulse width in response to temperature changes, the system maintains reliable operation timing despite environmental variations
2Reliability
If PMOS and NMOS transistors are used simultaneously in CMOS, then the driving circuit can function, but through current flows from power supply to ground causing power waste
Solution Approach 1:
The patent employs periodic control signals that alternately activate PMOS and NMOS transistors rather than allowing them to conduct simultaneously. This timing-based control ensures that only one transistor type conducts at any given moment, eliminating through current while maintaining necessary driving functionality
Solution Approach 2:
The control circuits generate driving signals with predetermined timing characteristics that prevent simultaneous conduction of PMOS and NMOS. By carefully designing the signal timing in advance, the system ensures that transistors are switched on and off in a sequence that avoids through current flow
3Productivity
If the LSI size increases and elements are miniaturized, then integration density improves, but variations in operation timings increase making it difficult to develop operable LSI
Solution Approach 1:
The patent implements delay detection circuits that measure actual signal propagation delays through the miniaturized circuit elements and feed this data back to control mechanisms. This feedback enables real-time compensation for timing variations introduced by small-size effects, maintaining operational reliability despite high integration density
Solution Approach 2:
The system uses its own delay detection capabilities to automatically identify and compensate for timing variations caused by miniaturization. The circuit self-adjusts its operation based on measured delays, eliminating the need for external calibration and maintaining timing consistency in high-density implementations
4Reliability
If cross-talk is avoided by modifying wiring or repositioning circuits, then signal integrity improves, but design complexity and revision requirements increase
Solution Approach 1:
The patent introduces control circuits as intermediary elements between signal sources and loads. These control circuits actively manage signal characteristics and timing to prevent cross-talk effects without requiring physical separation or complex wiring modifications, thereby maintaining signal integrity while simplifying layout design
Solution Approach 2:
The patent replaces physical layout solutions (such as increased spacing or shielding) with electronic control mechanisms. By using control circuits to actively manage signal behavior, the system achieves cross-talk prevention through electrical means rather than mechanical or physical design changes, reducing overall design complexity
Data Source
AI summary
In addition to two-stage CMOS inverters inverting and amplifying the input signal, a rising edge detector detects the rising edge of the input signal, and outputs a rising edge detection signal having a pulse width corresponding to ambient temperature, a PMOS drives the output node to the power supply potential according to the rising edge detection signal, a falling edge detector detects the falling edge of the input signal and outputs a falling edge detection signal having a pulse width corresponding to ambient temperature, and an NMOS drives the output node to ground potential according to the falling edge detection signal. When ambient temperature rises, and delay time of the inverters are thereby increased, pulse widths of the rising and falling edge detection signals are increased. The additional driving restrains delay time variation in a driving circuit due to ambient temperature change.