CMOS EEPROM Cell Design for Erase Performance
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Solution Overview
Problem
Existing EEPROM devices face challenges in achieving fast programming and data retention due to high process complexity, cost, and limited endurance, primarily because of the contradictory requirements for control gate capacitance during programming and erasing, which result in poor operational speed and data retention.
Innovation Solution
A CMOS compatible EEPROM memory cell design utilizing three NMOS transistors as control, erase, and program capacitors with a floating gate, featuring a coupling ratio of approximately 2:1, isolated by a Deep N Well structure, allowing for lower erase voltage and coupling ratio while maintaining erase speed through Fowler-Nordheim tunneling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If prior art stacked/split gate EEPROM technology is used, then erase performance can be achieved, but process complexity and manufacturing cost increase due to special multi-polysilicon materials, different gate oxide thicknesses, and modified doping profiles
Solution Approach 1:
The patent changes the fundamental parameters of the EEPROM structure by using a single polysilicon layer with uniform gate oxide thickness, replacing the prior art's multi-polysilicon stacked gate structure. This parameter change simplifies the manufacturing process while maintaining erase performance through a different structural approach using deep N-well isolation and specific transistor configurations.
Solution Approach 2:
The invention replaces expensive special multi-polysilicon materials and modified doping profiles with standard CMOS-compatible single polysilicon technology, effectively using cheaper, more readily available materials and processes that are already established in conventional CMOS manufacturing.
2Productivity
If control gate capacitance is increased for programming, then programming speed improves, but erase performance deteriorates due to the same capacitance requirement
Solution Approach 1:
The patent segments the capacitance function by introducing separate control capacitor and erase capacitor structures with different capacitance values. The control capacitor is optimized for programming operations while the erase capacitor is optimized for erase operations, allowing each function to have its own optimized capacitance without compromise.
Solution Approach 2:
The invention makes the capacitance configuration dynamic by using switching mechanisms that can selectively connect different capacitor structures during programming and erasing operations. This allows the effective capacitance to change based on the operation being performed, optimizing performance for each specific function.
3Ease of manufacture
If deep N Well isolation structure is implemented, then CMOS compatibility and process simplification are achieved, but additional manufacturing steps are required
Solution Approach 1:
The deep N-well structure serves multiple functions simultaneously: it provides isolation between PMOS and NMOS devices, enables CMOS compatibility, and creates the necessary potential wells for the EEPROM operation. This multi-functionality justifies the additional manufacturing step by consolidating several requirements into a single structural feature.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design significantly improves endurance by enabling up to 10,000 to 100,000 program/erase cycles, reduces chip size, and lowers operational voltage, enhancing the overall performance and endurance of EEPROM devices.
Implementation Method 1
the capacitance between the floating gate and the control gate should be large
Implementation Method 2
Electrons on the floating gate will pass through the gate oxide between the floating gate and the control gate by Fowler-Nordheim (FN) tunneling process and go to the substrate
Implementation Method 3
hot electrons are generated at the high electric field region at the drain junction
Implementation Method 4
injecting drain avalanche hot electrons into the floating gate
Data Source
AI summary
A system and method are disclosed for enhancing the performance of erase operations in CMOS compatible EEPROM memory cells. An EEPROM memory cell is described in which the erase voltage and the coupling ratio of the EEPROM memory cell are simultaneously decreased while maintaining the erase performance (e.g., erase speed) of the EEPROM memory cell. Significant improvement in the endurance of CMOS compatible EEPROM devices is obtained due to the enhanced erase performance of the EEPROM memory cells of the present invention.