CMOS EPROM Floating-Gate pFET Memory Element
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Solution Overview
Problem
Existing CMOS non-volatile memory devices face challenges with high programming voltage requirements and non-planar cell topography due to floating gate electrodes, as well as performance and power dissipation issues when using pFETs as select devices and floating-gate nFETs as memory elements.
Innovation Solution
The use of an nFET as the access transistor and a floating-gate pFET as the memory element, with a thick gate dielectric to prevent unwanted tunneling, allowing for efficient hot electron injection and reducing power dissipation, while maintaining compatibility with standard CMOS logic processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a floating gate electrode is used to store charges, then non-volatile memory function is achieved, but high programming voltage is required
Solution Approach 1:
The patent changes the material parameter of the gate dielectric from conventional thin oxide to thick oxide (e.g., 50-200 nm). This parameter change enables charge storage without requiring high programming voltage, as the thick oxide can be programmed through hot carrier injection at lower voltages while still preventing charge leakage
Solution Approach 2:
The patent uses a composite structure combining thick oxide dielectric with metal gate electrode. This composite material approach allows the device to achieve both non-volatile memory function and low programming voltage operation, as the metal gate provides high capacitance for efficient charge storage while the thick oxide prevents tunneling
2Quantity of substance
If a floating gate electrode is used, then charge storage capability is improved, but non-planar cell topography results
Solution Approach 1:
The patent replaces the physical floating gate electrode structure with an electrical equivalent model using thick oxide and metal gate. This copying approach maintains the charge storage functionality while eliminating the non-planar topography, allowing standard planar CMOS fabrication processes to be used
Solution Approach 2:
The patent substitutes the mechanical/physical floating gate electrode structure with an electrical field-based charge storage mechanism using thick oxide. This substitution eliminates the need for complex three-dimensional electrode structures while maintaining charge storage capability
3Area of stationary object
If pFET is used as access transistor, then device area is reduced, but access transistor speed decreases
Solution Approach 1:
The patent inverts the conventional approach by using nFET as the access transistor instead of pFET. This inversion allows the use of high-speed nFET for access while the thick-oxide pFET serves as the memory element, achieving both fast access speed and compact area
4Reliability
If floating-gate nFET is used as memory element, then memory function is achieved, but power dissipation increases
Solution Approach 1:
The patent inverts the conventional configuration by using floating-gate pFET instead of nFET as the memory element. This inversion reduces power dissipation because pFETs have lower leakage currents and can be programmed with lower power, while maintaining full memory functionality through the thick oxide charge storage mechanism
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances memory device performance by reducing programming voltage, improving access transistor speed, and increasing memory density, while maintaining high reliability and data integrity.
Implementation Method 1
it takes a lower voltage to inject hot electrons from silicon into a floating gate electrode than to inject electrons from silicon into a floating gate electrode by Fowler-Nordheim tunneling
Implementation Method 2
hot electron injection is typically used
Implementation Method 3
it is much more efficient to use avalanche hot electron injection using a p-channel FET device
Data Source
AI summary
A CMOS EPROM, EEPROM or inverter device includes an nFET device with a thin gate dielectric layer and a pFET device juxtaposed with the nFET device with a thick gate dielectric layer and a floating gate electrode. The thick gate dielectric layer is substantially thicker than the thin gate dielectric layer. A common drain node connected both FET devices has no external connection in the case of a memory device and has an external connection in the case of an inverter. There are external circuit connections to the source regions of both FET devices and to the gate electrode of the nFET device. The pFET and nFET devices can be planar, vertical or FinFET devices.