CMOS ETSOI Triple Well Structure for Independent Back Gate Biasing
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Solution Overview
Problem
Current semiconductor fabrication techniques face challenges in simultaneously achieving different back gate doping types and biases for transistors, leading to issues with threshold voltage control, leakage, and process variations, particularly in thin silicon on insulator (SOI) technology.
Innovation Solution
The implementation of a triple well back gate structure with dual-depth insulating isolation, featuring shallow intra-well and deep inter-well STI, allows for independent biasing of nFETs and pFETs, reducing leakage and enabling flexible threshold voltage adjustment by using different back gate doping types and biases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single BOX SOI wafer is used with uniform doping, then fabrication is simplified, but different back gate doping types and biases cannot be achieved
Solution Approach 1:
The patent divides the single BOX SOI wafer into multiple independently biasable regions by introducing deep isolation regions that extend through the BOX layer. This segmentation allows different back gate doping types and biases to be applied to different transistor regions while maintaining overall fabrication simplicity.
Solution Approach 2:
The patent implements local quality by creating regions with different doping types (n-type and p-type) and different isolation depths within the same wafer. Shallow isolation regions separate adjacent transistors of the same type, while deep isolation regions separate transistors requiring different biases, allowing each region to have optimized properties for its specific function.
2Reliability
If shallow isolation regions are used only, then adjacent transistor isolation is achieved, but well region separation for different biases is not possible
Solution Approach 1:
The patent extends the isolation concept into the vertical dimension by creating deep isolation regions that penetrate through the BOX layer, whereas conventional shallow isolation only extends partway into the BOX. This additional depth dimension enables independent well biasing while maintaining the shallow isolation benefit for adjacent transistor separation.
Solution Approach 2:
The patent segments the isolation structure into two distinct types: shallow isolation regions for adjacent transistor separation and deep isolation regions for well region separation. This segmentation allows each isolation type to perform its specific function independently, achieving both transistor isolation and independent well biasing.
3Adaptability or versatility
If deep isolation regions extend through BOX layer, then well region separation is achieved, but fabrication complexity increases
Solution Approach 1:
The patent applies deep isolation regions only where needed to separate well regions requiring different biases, rather than applying deep isolation uniformly across the entire wafer. This localized application reduces overall fabrication complexity while maintaining the necessary well separation capability.
Solution Approach 2:
The patent segments the isolation strategy by using shallow isolation as the default for most adjacent transistor pairs, and selectively applying deep isolation only where well separation is required. This segmentation reduces the total number of deep isolation regions needed, thereby reducing fabrication complexity.
Data Source
AI summary
A semiconductor substrate having a first type of conductivity and a top surface, a layer of oxide disposed over the top surface and a semiconductor layer disposed over the layer of oxide. A plurality of transistor devices are disposed upon the semiconductor layer. Each transistor device includes a channel between a source and a drain, where some transistor devices have a first type of channel conductivity and the remaining transistor devices have a second type of channel conductivity. A well region is formed adjacent to the top surface. The well region has a second type of conductivity. First trench isolation regions are between adjacent transistor devices that extend through the semiconductor layer. Second trench isolation regions are between adjacent transistor devices of opposite channel conductivity.