CMOS Fabrication Process for PMOS Transistor Defect Reduction
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Solution Overview
Problem
P-channel MOS transistors in CMOS integrated circuits face issues with end of range defects and leakage current due to shrinking transistor sizes, which are not effectively addressed by existing ultra high temperature (UHT) processes, and are incompatible with stress memorization techniques (SMT) used for n-channel transistors.
Innovation Solution
Forming p-type source and drain regions in PMOS transistors before n-type regions in NMOS transistors, using a pre-amorphization implant and carbon co-implant, followed by an ultra high temperature anneal above 1200 C for less than 100 milliseconds, and applying tensile stress through a stress memorization technique layer deposited after the anneal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If UHT annealing is performed after deposition of the SMT layer, then end of range defects are reduced, but the SMT layer hardens and removal becomes problematic
Solution Approach 1:
The patent performs the UHT annealing action before depositing the SMT layer, eliminating end of range defects in advance. This preliminary defect reduction occurs on the PSD regions without the SMT layer present, avoiding any hardening effect that would complicate subsequent layer removal.
Solution Approach 2:
The patent inverts the conventional sequence by performing UHT annealing before SMT layer deposition rather than after. This reversal of the process order eliminates the harmful hardening effect while still achieving defect reduction, as the anneal occurs on the substrate without the organic SMT layer that would otherwise harden at high temperature.
2Reliability
If temperatures above 1200 C are used in rapid thermal anneal to annihilate end of range defects, then defects are reduced, but unacceptably high spreads in spatial distributions of boron dopants occur
Solution Approach 1:
The patent changes the temperature parameter to exactly 1200°C, which is the threshold temperature that provides sufficient thermal energy to annihilate end of range defects while being low enough to minimize boron dopant diffusion. This precise parameter selection optimizes the trade-off between defect reduction and dopant spatial distribution control.
Solution Approach 2:
The patent applies exactly the minimum necessary temperature (1200°C) to achieve defect annihilation without excessive heating. This partial action approach provides just enough thermal energy to repair end of range defects while avoiding the excessive temperature that would cause unacceptable boron diffusion and spatial distribution spreads.
3Manufacturing precision
If n-type source and drain regions are formed before p-type regions, then thermal profile on implanted dopants in PSD regions is minimized, but this conventional sequence does not address end of range defects in PSD regions
Solution Approach 1:
The patent performs UHT annealing on PSD regions as a preliminary action before subsequent NMOS processing steps. This preliminary defect reduction ensures that end of range defects are eliminated early in the process, and the subsequent formation of NMOS regions can proceed with standard thermal profiles without compromising PSD region quality.
Solution Approach 2:
The patent applies UHT annealing selectively and locally to PSD regions only, using spatially selective processing to treat PMOS drain regions with high temperature while leaving NMOS regions unaffected. This local treatment reduces end of range defects in PSD regions without requiring a global change in process sequence that would affect NMOS dopant thermal profiles.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Significantly reduces end of range defects and enhances transistor performance by minimizing leakage current and maintaining the effectiveness of the stress memorization technique for n-channel transistors.
Implementation Method 1
the PSD regions are implanted with a pre-amorphization implant (PAI) and a carbon species co-implant
Implementation Method 2
annealed with an ultra high temperature (UHT) process above 1200 C for less than 100 milliseconds
Implementation Method 3
tensile stress is applied to the NMOS gate by a stress memorization technique (SMT) layer which is deposited after the PSD UHT anneal
Data Source
AI summary
Ultra high temperature (UHT) anneals above 1200 C for less than 100 milliseconds for PMOS transistors reduce end of range dislocations, but are incompatible with stress memorization technique (SMT) layers used to enhance NMOS on-state current. This invention reverses the conventional order of forming the NMOS first by forming PSD using carbon co-implants and UHT annealing them before implanting the NSD and depositing the SMT layer. End of range dislocation densities in the PSD space charge region below 100 cm−2 are achieved. Tensile stress in the PMOS from the SMT layer is significantly reduced. The PLDD may also be UHT annealed to reduce end of range dislocations close to the PMOS channel.