Planar CMOS FET Insulating Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
Existing planar complementary metal oxide semiconductor field effect transistors (CMOS FETs) face challenges in reducing parasitic capacitance, which increases power consumption due to diffused source/drains inducing capacitance between the source/drain region and the substrate.
Innovation Solution
The implementation of air spacers and embedded insulating layers below the source/drain diffusion regions and gate electrode, formed through specific etching and ion implantation processes, to suppress or eliminate parasitic capacitance, thereby reducing power consumption and enhancing device speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If diffused source/drains are used in planar CMOS FETs, then manufacturing is simplified, but parasitic capacitance between source/drain region and substrate increases
Solution Approach 1:
The patent introduces air spacers positioned beneath the source/drain diffusion regions, transitioning from a two-dimensional planar structure to a three-dimensional structure with vertical separation. This dimensional change creates physical distance between the source/drain regions and the substrate, reducing parasitic capacitance while maintaining manufacturing simplicity through standard semiconductor fabrication processes.
Solution Approach 2:
The patent employs air spacers as intermediary elements between the source/drain diffusion regions and the substrate. These air spacers act as dielectric mediators that reduce the capacitive coupling between the conductive source/drain regions and the substrate, thereby reducing parasitic capacitance without complicating the manufacturing process.
2Use of energy by moving object
If parasitic capacitance is reduced to lower power consumption, then energy efficiency improves, but device structure becomes more complex
Solution Approach 1:
The patent segments the substrate region beneath the source/drain diffusion areas by introducing air spacers that create isolated air gaps. This segmentation separates the source/drain regions from direct contact with the substrate, reducing parasitic capacitance and power consumption while adding minimal structural complexity through a modular approach that can be integrated into existing device architectures.
3Object-generated harmful factors
If air spacers and embedded insulating layers are implemented, then parasitic capacitance is reduced, but manufacturing process complexity increases
Solution Approach 1:
The patent implements air spacers and embedded insulating layers as preliminary structural elements before forming the source/drain diffusion regions. By pre-positioning these capacitance-reducing features, the manufacturing process integrates smoothly with standard semiconductor fabrication sequences, reducing parasitic capacitance without significantly increasing overall process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance, leading to lower power consumption and improved semiconductor device performance, including increased speed and reduced manufacturing costs by eliminating the need for costly silicon-on-insulator (SOI) wafers.
Implementation Method 1
reducing parasitic capacitance is one of the key technologies. Existing planar complementary metal oxide semiconductor field effect transistors (CMOS FETs) have diffused source/drains (S/D) that induce parasitic capacitance between the S/D region and the substrate
Data Source
AI summary
A semiconductor device including a FET includes an isolation insulating layer disposed in a trench of the substrate, a gate dielectric layer disposed over a channel region of the substrate, a gate electrode disposed over the gate dielectric layer, a source and a drain disposed adjacent to the channel region, and an embedded insulating layer disposed below the source, the drain and the gate electrode and both ends of the embedded insulating layer are connected to the isolation insulating layer.