CMOS FinFET Device with Segmented III-V and Ge Fins
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Solution Overview
Problem
Existing FinFET devices face challenges in achieving optimal carrier mobility and complexity in manufacturing due to the scaling down process in semiconductor technology, which affects the performance and efficiency of integrated circuits.
Innovation Solution
A method for fabricating a CMOS FinFET device involving the formation of fin structures with alternating III-V and Ge materials, where III-V material is epitaxially grown over one region and Ge over the other, with a gate structure separating source and drain regions, enhancing carrier mobility and device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional FinFET devices are used with conventional materials, then manufacturing process is simpler, but carrier mobility is insufficient for high-performance applications
Solution Approach 1:
The fin structure is segmented into multiple regions (first region, second region, third region) with different material compositions. The channel region contains SiGe material while source/drain regions contain different compositions, allowing optimized carrier mobility in the channel while maintaining manufacturability through systematic material distribution
Solution Approach 2:
Different material compositions are applied to different regions of the fin structure. The channel region receives SiGe material with specific germanium content (10-30%) to enhance carrier mobility locally, while source and drain regions have different compositions, creating localized material properties matched to functional requirements
2Productivity
If geometry size is scaled down to increase device density, then production efficiency and cost are improved, but manufacturing complexity and performance optimization become more difficult
Solution Approach 1:
The material composition parameter is changed by introducing SiGe alloys with varying germanium percentages (10-30%) in the channel region. This parameter change enables continued scaling to smaller geometries while maintaining or improving carrier mobility, offsetting the negative effects of dimension reduction through compositional modification
3Reliability
If conventional materials are used in FinFET devices, then manufacturing process is less complex, but intrinsic carrier mobility is limited and device performance suffers
Solution Approach 1:
SiGe composite materials are used in the fin channel region, combining silicon with germanium to create an alloy with superior carrier mobility properties. This composite material approach achieves 4-6 times improvement in intrinsic carrier mobility compared to pure silicon, while the deposition process integrates into existing manufacturing workflows
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly improves intrinsic carrier mobility by approximately 4 times for NMOS and 6 times for PMOS FinFET devices compared to traditional FinFETs, addressing the limitations of existing technologies while maintaining manufacturing complexity.
Implementation Method 1
a second portion of the first fin comprises a III-V semiconductor material grown over a surface of the first fin
Implementation Method 2
a second portion of the second fin comprises a Ge material grown over a surface of the second fin
Data Source
AI summary
A CMOS FinFET device and method for fabricating a CMOS FinFET device is disclosed. An exemplary CMOS FinFET device includes a substrate including a first region and a second region. The CMOS FinFET further includes a fin structure disposed over the substrate including a first fin in the first region and a second fin in the second region. The CMOS FinFET further includes a first portion of the first fin comprising a material that is the same material as the substrate and a second portion of the first fin comprising a III-V semiconductor material deposited over the first portion of the first fin. The CMOS FinFET further includes a first portion of the second fin comprising a material that is the same material as the substrate and a second portion of the second fin comprising a germanium (Ge) material deposited over the first portion of the second fin.