CMOS Flash ADC Layout for Mismatch and Power
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Solution Overview
Problem
Conventional flash analog-to-digital converters (ADCs) face challenges with high power dissipation, large silicon area consumption, and high manufacturing costs due to their reliance on bipolar junction transistors (BJTs), while CMOS-based ADCs suffer from transistor mismatch errors leading to differential non-linearity issues and code misplacements.
Innovation Solution
A physical layout for an ADC with comparators arranged in a one-dimensional row configuration, where neighboring comparators are positioned orthogonally, reducing transistor mismatch and improving matching characteristics, and utilizing CMOS processes to minimize power dissipation and die size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional flash ADCs use BJT technology to achieve fast conversion rates, then conversion speed is improved, but power dissipation and die size increase significantly
Solution Approach 1:
The patent changes the transistor technology parameter from BJT to CMOS, fundamentally altering the electrical characteristics to achieve lower power dissipation while maintaining competitive conversion speeds through optimized comparator circuit design and layout
2Speed
If conventional flash ADCs use BJT technology to achieve fast conversion rates, then conversion speed is improved, but die size and manufacturing cost increase
Solution Approach 1:
The patent changes the transistor technology parameter from BJT to CMOS, which inherently occupies less silicon area per transistor, and further optimizes the layout by arranging comparators in a compact array with shared reference structures to minimize overall die size
3Loss of energy
If CMOS processes are used to reduce power dissipation and die size, then power efficiency is improved, but transistor mismatch errors increase causing differential non-linearity
Solution Approach 1:
The patent segments the comparator design into matched pairs of transistors with identical geometry and layout positioning, ensuring that mismatch errors are minimized through symmetry and that differential non-linearity is reduced while maintaining CMOS power efficiency
4Measurement precision
If more comparators are added to increase ADC resolution, then conversion accuracy is improved, but power dissipation and die size increase
Solution Approach 1:
The patent merges adjacent comparators by sharing common reference voltage taps from the resistor string and combining output logic functions, allowing higher resolution ADC operation with reduced total comparator count and associated power dissipation
Data Source
AI summary
Physical layouts of integrated circuits are provided, which may include an analog-to-digital converter including a plurality of comparators. Individual transistors of each comparator of the plurality are arranged in a one-dimensional row in a first direction. Neighboring comparators of the plurality of comparators are positioned relative to each other in an abutting configuration in a second direction orthogonal to the first direction. The plurality of comparators may include multiple, inter-coupled outputs. Such an ADC may be called a Benorion Analog-to-Digital Converter. A method for fabricating an integrated circuit is also provided. The method comprises arranging transistors of a first comparator in a one-dimensional row in a first direction, arranging transistors of at least one additional comparator in the one-dimensional row in the first direction, and arranging transistors of the first comparator and the at least one additional comparator relative to each other in a second direction orthogonal to the first direction.