CMOS Image Sensor Floating Diffusion Hollow Region Capacitance
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Solution Overview
Problem
In CMOS image sensors, the miniaturization of pixels leads to reduced photodiode opening areas, lower sensitivity, and degraded image quality due to increased parasitic capacitance, which complicates the reduction of floating diffusion (FD) wiring capacitance without compromising noise levels.
Innovation Solution
Creating a hollow region between the FD wiring and other wirings in the CMOS image sensor to reduce capacitance, utilizing a low dielectric constant film in the wiring interlayer and forming hollow regions around the FD wiring to decrease parasitic capacitance without affecting mechanical strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the size of the pixel transistor is reduced to improve integration, then device complexity is reduced, but random noise worsens and reliability decreases
Solution Approach 1:
The patent extracts the disturbing element (parasitic capacitance of FD wiring) by creating a hollow region around the FD wiring. This removes the harmful capacitive coupling between the FD wiring and other wirings, allowing the pixel transistor to be miniaturized without suffering from increased random noise due to parasitic capacitance effects.
2Productivity
If the opening area of photodiode is reduced for miniaturization, then productivity increases, but sensitivity decreases and image quality degrades
Solution Approach 1:
The patent removes the harmful parasitic capacitance of the FD wiring by creating a hollow region around it. This extraction of the harmful capacitive element allows for reduced pixel size and photodiode opening area while maintaining sensitivity, as the parasitic capacitance that would otherwise degrade the signal is eliminated.
3Object-affected harmful factors
If the capacitance of FD wiring is reduced by lowering N-type impurity concentration, then parasitic capacitance decreases, but contact failure risk increases
Solution Approach 1:
Instead of reducing the N-type impurity concentration of the FD (which would risk contact failure), the patent takes out the harmful parasitic capacitance by creating a hollow region around the FD wiring. This physically removes the source of parasitic capacitance while maintaining the electrical properties of the FD and its contacts.
4Object-affected harmful factors
If the size of amplifying transistor is reduced to decrease gate electrode capacitance, then parasitic capacitance decreases, but random noise worsens
Solution Approach 1:
The patent removes the harmful parasitic capacitance of the FD wiring by creating a hollow region around it. This extraction eliminates the need to reduce the amplifying transistor size to decrease gate electrode capacitance, as the primary source of parasitic capacitance (the FD wiring) is already removed. Consequently, the amplifying transistor can maintain a larger size for better noise performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces capacitance, improves charge-voltage conversion efficiency, and enhances image quality by minimizing noise propagation while maintaining mechanical strength and allowing for high-speed pixel signal processing.
Implementation Method 1
at least a part of a region between an FD wiring connected to a floating diffusion and a wiring other than the FD wiring is a hollow region
Data Source
AI summary
The present disclosure relates to a solid-state image-capturing element and an electronic device capable of reducing the capacitance by using a hollow region. At least a part of a region between an FD wiring connected to a floating diffusion and a wiring other than the FD wiring is a hollow region. The present disclosure can be applied to a CMOS image sensor having, for example, a floating diffusion, a transfer transistor, an amplifying transistor, a selection transistor, a reset transistor, and a photodiode.