CMOS Signal Formatter Using Current Steering for Precise ATE Waveforms
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Automatic test equipment for high-speed digital signals faces challenges in generating precise waveform formats efficiently while consuming low power, as existing formatters often require complex circuitry and high power consumption.
Innovation Solution
A fast, low-power formatter is developed using multiple signal paths with pulse shrinking and current steering circuits to selectively alter signals, allowing for efficient combination of edge signals and reducing power consumption by implementing the formatter in CMOS technology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If traditional SR latch based formatter is used, then waveform formatting function is achieved, but power consumption is high
Solution Approach 1:
The formatter is divided into multiple independent signal paths (first signal path, second signal path, etc.), each handling specific edge signals. This segmentation allows parallel processing of multiple edges simultaneously, maintaining high productivity while using simple CMOS circuitry in each path to reduce overall power consumption.
Solution Approach 2:
The patent replaces traditional complex formatter circuitry with CMOS-based pulse shrinking circuits and current steering circuits. This substitution uses standard semiconductor technology instead of specialized high-power components, achieving the same waveform formatting function with significantly reduced power consumption.
2Manufacturing precision
If complex circuitry is used to generate precise waveforms, then waveform precision is improved, but device complexity increases
Solution Approach 1:
The patent uses dynamic current steering circuits that can rapidly switch between different signal paths based on format data. This dynamic approach allows precise control of waveform edges without requiring complex static circuitry, achieving high waveform precision with simpler overall device design.
Solution Approach 2:
The formatter uses pulse shrinking circuits that dynamically adjust pulse width parameters based on the desired waveform format. By changing the temporal parameters of edge signals rather than using complex circuit topologies, the patent achieves precise waveform generation with simpler circuitry.
Data Source
AI summary
Automated test equipment (ATE) used to test semiconductor components during the manufacturing process. The ATE generates and measures signals at test points of a device under test. The ATE includes a signal formatter with an SR latch having set an reset inputs each connected through or coupled to a number of signal channels. Each signal channel may receive a long pulse from a timing generator and generate a short pulse. Each signal channel has a current steering circuit that couples the short pulses to the set or reset ports of the latch. Because the outputs of each current steering circuit have a high impedance when not sending a pulse, multiplexing circuitry and/or circuitry to logically OR the outputs of separate signal channels are unnecessary. The hardware eliminated by this design simplifies and improves the ATE. Additionally, the latch can be set and reset in quick succession with good timing resolution.