CMOS Sensor Column Gain Mismatch Correction

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Solution Overview

Problem

CMOS imaging Systems-on-Chip (iSoC) sensors are prone to column gain mismatch issues, leading to artifacts in images due to finite offset and gain deviations at analog buffer stages, which conventional digital corrections often fail to adequately address, especially under low-light conditions and high photon fluxes.

Innovation Solution

The implementation of tunable voltages to test pixels in a CMOS sensor imager, allowing for column-specific digital gain corrections to be calibrated and applied, using optical black pixels for noise calibration and memory-retained correction values to mitigate column gain mismatch.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional digital corrections are used to align offsets, then offset alignment is improved, but column gain variations are not corrected, degrading flat field image quality

Engineering Contradiction:
Improveoffset alignment precisionVSAvoidflat field image quality
Core Design Contradiction:
Measurement precisionVSManufacturing precision

Solution Approach 1:

The patent applies parameter changes by transitioning from simple offset alignment to gain correction. Specifically, it calculates column-specific gain correction factors by comparing actual pixel values to expected values from test patterns, then applies these gain factors to correct the image data. This changes the correction parameter from offset only to gain, resolving the contradiction between offset alignment and flat field quality.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent implements feedback by using test pixels and test patterns to measure actual column response, comparing it to expected response, and using this feedback to calculate correction factors. The system reads test patterns, computes actual vs expected values, derives gain correction factors, and applies them to correct subsequent image data, creating a closed-loop feedback correction system.

Inventive Principle:
Principle #23Feedback

2Strength

If high gain is applied in low-light conditions, then signal strength is improved, but column FPN artifacts become more visible

Engineering Contradiction:
Improvesignal strengthVSAvoidcolumn FPN visibility
Core Design Contradiction:
StrengthVSObject-affected harmful factors

Solution Approach 1:

The patent converts the harmful effect of gain mismatch into a correctable parameter by measuring it through test patterns and applying digital correction. The gain mismatch that creates visible artifacts is quantified using test pixels and correction factors, then digitally reversed to produce flat field images even under high gain conditions.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The patent applies preliminary action by performing calibration using test patterns and calculating gain correction factors before capturing the actual image data. This preliminary measurement and computation of correction factors allows the system to compensate for gain variations in subsequent imaging operations, preventing FPN artifacts from degrading image quality.

Inventive Principle:
Principle #10Preliminary action

3Ease of operation

If rudimentary digital corrections are applied, then offset alignment is achieved, but gain variations are not accounted for

Engineering Contradiction:
Improvecorrection simplicityVSAvoidimage quality
Core Design Contradiction:
Ease of operationVSManufacturing precision

Solution Approach 1:

The patent extends the correction approach by changing from simple offset alignment to gain correction. It calculates column-specific gain factors by analyzing test pixel responses to test patterns, then applies these gain correction factors to the image data. This parameter change from offset to gain correction addresses the limitation of rudimentary corrections while maintaining operational simplicity through automated processing.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8094215B2Digital column gain mismatch correction for 4T CMOS imaging systems-on-chip
Publication Date: 2012.01.10 SAMSUNG ELECTRONICS CO LTD
  • US8094215B2 patent drawing
  • US8094215B2 patent drawing
  • US8094215B2 patent drawing

AI summary

Systems and methods are provided that facilitate mitigating column gain mismatch in a CMOS imaging System-on-Chip (iSoC) sensor. Tunable voltages that mimic presence of photo-charge can be provided to test pixels in one or more rows of a pixel array. Moreover, column-specific digital gain corrections can be calibrated based upon input data received from the test pixels. During calibration, actual data can be compared to a target expected to be obtained via an analog readout architecture. The calibrated, column-specific digital gain corrections can be utilized to correct for column gain mismatch to yield output data. Further, correction values corresponding to the column-specific digital gain corrections can be retained in and retrieved from memory. The correction values, for example, can be a function of a scaling parameter that is tuned to match an available memory dynamic to a range of uncorrected gain mismatch.