CMOS Gate Bias Reduction via Differential N+ Poly Doping
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Solution Overview
Problem
The existing CMOS processing flows result in unintended CD differentials between PMOS and NMOS transistors due to poly etch rate differences, leading to degradation in PMOS performance, particularly in SRAM cells, where n+ poly doping can cause counterdoping and increased TOXINV, affecting VTLIN/VTSAT control and device performance.
Innovation Solution
The method involves skipping the pre-gate etch n+ poly implant step, patterning polysilicon gates while undoped, and performing n-type doping after the spacer process, with specific implant doses and masking to prevent n+ poly doping in PMOS regions, thereby reducing CD delta and maintaining balanced doping levels across NMOS and PMOS transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If n+ poly pre-gate etch doping mask is used to raise dopant level in polysilicon for NMOS area, then NMOS transistor performance is improved, but unintended CD differential between PMOS and NMOS is created due to poly etch rate differences
Solution Approach 1:
The patent divides the polysilicon doping process into two separate implantation steps: (1) source/drain region doping that provides base dopant level to all polysilicon, and (2) selective pre-gate etch doping that raises dopant level only in NMOS polysilicon gates. This segmentation allows differential doping without creating unintended CD variations, as each region receives precisely the dopant amount it requires through controlled masking and implantation sequences.
Solution Approach 2:
The patent applies local quality by creating different dopant levels in different polysilicon regions through selective masking. The n+ poly pre-gate etch doping mask is specifically positioned to cover only PMOS polysilicon regions during the second implantation step, ensuring that NMOS polysilicon gates receive higher dopant concentration while PMOS polysilicon gates maintain lower dopant concentration, thus achieving locally optimized transistor performance.
2Reliability
If n-type dopant is implanted into polysilicon gates for NMOS to reduce TOXINV, then inversion charge loss is reduced, but counterdoping of PMOS gates occurs affecting VTLIN/VTSAT control
Solution Approach 1:
The patent uses an intermediary masking layer (n+ poly pre-gate etch doping mask) that acts as a protective barrier during the dopant implantation process. This mask is deposited conformally over the polysilicon surface and selectively removed to expose only NMOS polysilicon gate regions for additional n-type doping, thereby preventing dopant contamination of PMOS gates while enabling TOXINV reduction in NMOS devices through controlled intermediate protection and selective exposure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces TOXINV, enhances PMOS performance, improves stability and yield in SRAM cells, and allows for tighter design rules, maintaining balanced transistor performance without degrading NMOS performance, thus addressing the counterdoping issues and scaling challenges.
Implementation Method 1
an n-type dopant (e.g. P or As) is implanted into the polysilicon gates corresponding to the NMOS area
Implementation Method 2
A dopant anneal may or may not follow the n-type poly pre-gate doping
Data Source
AI summary
A method of fabricating a CMOS integrated circuit includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric layer on the semiconductor surface and a polysilicon layer on the gate dielectric layer. The polysilicon layer is patterned while being undoped to form a plurality of polysilicon comprising gates. A first pattern is used to protect a plurality of PMOS devices and a first n-type implant is performed to dope the gates and source/drain regions for a plurality of NMOS devices. A second pattern is used to protect the PMOS devices and the sources/drains and gates for a portion of the plurality of NMOS devices and a second n-type implant is performed to dope the gates of the other NMOS devices.