CMOS Transmission Gate Feedback for Parasitic Capacitance
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Solution Overview
Problem
Semiconductor switches in CMOS technology face issues with parasitic capacitance, which cause signal attenuation at higher frequencies due to increased impedance and unwanted capacitance, limiting the maximum frequency of switched signals.
Innovation Solution
The solution involves sensing the rate of change of voltage (dv/dt) using an RC network and an operational transconductance amplifier (OTA) to measure and scale the current through parasitic capacitances, then feeding back a current of opposite polarity from the local power supply into the signal path to reduce effective capacitance, thereby compensating for parasitic capacitance effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If larger transistors are used to reduce on-resistance, then lower resistive impedance is achieved, but parasitic capacitance increases
Solution Approach 1:
The patent applies feedback by sensing the rate of change of voltage (dv/dt) across the switch and injecting a compensating current of opposite polarity into the input node. This feedback mechanism dynamically counteracts the effect of parasitic capacitance, allowing the use of larger transistors for lower on-resistance without suffering from excessive capacitance effects at high frequencies.
Solution Approach 2:
The patent introduces an intermediary current injection mechanism that acts as a mediator between the parasitic capacitance effect and the signal. By injecting a current proportional to dv/dt through a transconductance amplifier, the system compensates for the capacitive current, effectively decoupling the signal from the harmful capacitive effects while maintaining the beneficial low on-resistance.
2Speed
If higher signal frequency is used, then faster signal propagation is achieved, but current required to charge and discharge parasitic capacitance increases
Solution Approach 1:
The feedback mechanism senses dv/dt and injects a compensating current that reduces the net current required to charge and discharge the parasitic capacitance. This allows higher signal frequencies to be achieved with reduced current consumption, as the compensating current offsets the capacitive current demand.
3Ease of operation
If parasitic capacitance is present, then switch functionality is maintained, but signal isolation deteriorates at higher frequencies
Solution Approach 1:
The feedback mechanism continuously compensates for the parasitic capacitance effect by injecting a current proportional to dv/dt. This dynamic compensation maintains signal isolation at higher frequencies while preserving the switch's basic functionality, effectively extending the useful frequency range of the switch.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively minimizes parasitic capacitance effects, improving signal isolation and frequency handling capabilities of the switches by reducing the current required to charge and discharge capacitances, thereby enhancing the switch's performance at higher frequencies.
Implementation Method 1
an operational transconductance amplifier (OTA) to measure and scale the current through parasitic capacitances
Implementation Method 2
parasitic capacitance effects... current through parasitic capacitances... i=C·dv/dt
Implementation Method 3
sensing the rate of change of voltage (dv/dt) using an RC network... to measure and scale the current through parasitic capacitances
Data Source
Figure 1A~1B
Figure 2A~3A
Figure 3B~3C
AI summary
A CMOS transmission gate that is compensated for lost current to parasitic capacitance. Parasitic capacitance current is detected by an amplifier and fed back in-phase to the input of the CMOS transmission gate with the gain of the amplifier set to avoid circuit instability. In a first example a transconductance amplifier detects a voltage drop across a resistor in and RC network and the resulting current applied to the input of the transmission gate. A second example uses a current amplifier to detect gate current of the N-channel and P-channel transistors of the transmission gate, and an output current is fed back in phase to the input of the CMOS transmission gate.