CMOS Gate Conductor Interconnect via Isolation Region Exposure
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Solution Overview
Problem
As semiconductor devices are scaled to smaller dimensions, the etch process for removing the dielectric cap layer from the gate structure becomes challenging, leading to degraded yield and damaged dielectric spacers, which affects the performance and controllability of field effect transistors.
Innovation Solution
The method involves removing a portion of the dielectric cap layer to expose the underlying semiconductor gate conductor layer on an isolation region and forming an interconnect directly with this exposed portion, ensuring that the active regions are protected from damage during the process, thereby maintaining the integrity of the gate structure and spacers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the dielectric cap layer is removed from the gate structure using conventional etch processes, then electrical connections can be formed to the gate, but the gate structures and dielectric spacers are damaged
Solution Approach 1:
The patent applies local quality by selectively removing the dielectric cap layer only in specific regions where electrical connections are needed, while preserving the cap layer over active regions to protect underlying structures. This localized approach allows etching to proceed without damaging gate structures and dielectric spacers in protected areas, resolving the contradiction between forming electrical connections and maintaining manufacturing precision.
2Ease of manufacture
If the dielectric cap layer is completely removed to form electrical connections, then interconnect access is achieved, but yield is degraded due to damage to gate structures
Solution Approach 1:
The patent segments the dielectric cap layer removal process into distinct regions: areas where the cap is removed to expose gate conductor layers for electrical connections, and areas where the cap is retained to protect underlying gate structures and dielectric spacers. This segmentation enables selective access to interconnects while preserving device integrity, thereby improving yield without compromising interconnect formation.
3Area of moving object
If scaling is continued to achieve higher integration density, then compactness is improved, but etch process controllability is lost
Solution Approach 1:
The patent applies preliminary action by forming the dielectric cap layer structure before subsequent etching operations. This pre-formed cap layer serves as a protective mask that guides the etching process, ensuring that only intended regions are exposed while critical structures remain protected. This preliminary protective structure enables continued scaling while maintaining etch process controllability and manufacturing precision.
Data Source
AI summary
A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region.