CMOS Gate Contact Structure for Misalignment and Leakage Control

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In CMOS fabrication, the shrinking technology nodes pose challenges such as misalignment of contacts leading to source/drain regions shorting to metal gate structures, exacerbated by decreasing gate length and spacing, which complicates the implementation of high-dielectric-constant gate dielectric layers and metal gate electrodes.

Innovation Solution

A method for fabricating semiconductor devices involves forming a helmet layer over the gate electrode, followed by a bottom conductive feature and contact etch stop layer, with a high-k dielectric layer and metal gate electrode formation using advanced patterning and deposition processes, including photolithography, ion implantation, and chemical mechanical polishing, to ensure precise alignment and reduced gate leakage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If gate length and spacing are decreased to shrink technology nodes, then device density and integration are improved, but misalignment of contacts occurs leading to source/drain regions shorting to metal gate structures

Engineering Contradiction:
Improvedevice densityVSAvoidcontact alignment
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

A helmet layer is formed over the gate electrode before contact formation to pre-establish a protective structure that defines the contact etch stop layer position, ensuring proper alignment before subsequent contact opening processes

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The helmet layer acts as an intermediary structure between the gate electrode and the contact etch stop layer, providing a reference plane that mediates the alignment between contacts and gate structures during etching processes

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If high-dielectric-constant gate dielectric layers are used to reduce gate leakage, then gate leakage is reduced, but device complexity and fabrication difficulty increase

Engineering Contradiction:
Improvegate leakageVSAvoidfabrication process
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The gate dielectric structure is segmented into multiple layers including a first dielectric layer and a second dielectric layer with different dielectric constants, allowing each layer to be optimized independently for leakage prevention and fabrication compatibility

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different dielectric materials are used in different regions of the gate stack - a high-k dielectric layer for leakage prevention and a lower-k dielectric layer for fabrication compatibility, creating local quality variations that solve both problems

Inventive Principle:
Principle #3Local quality

3Reliability

If metal gate electrodes are implemented to improve device performance, then device performance is improved, but subsequent high-temperature processing steps are reduced which may affect other device characteristics

Engineering Contradiction:
Improvedevice performanceVSAvoidprocessing temperature
Core Design Contradiction:
ReliabilityVSTemperature

Solution Approach 1:

Source/drain regions are formed before metal gate electrode formation, allowing these regions to be processed at required temperatures before the metal gate is deposited, preventing subsequent high-temperature processing of the metal gate

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the precision and reliability of contact formation, reduces gate leakage, and allows for more compact device dimensions by maintaining effective gate thickness while minimizing the number of subsequent high-temperature processing steps.

Implementation Method 1

forming a helmet layer over the gate electrode

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 2

ion implantation

Methodology Applied
Scientific EffectIon Implantation: Ion Implantation

Implementation Method 3

chemical mechanical polishing

Methodology Applied
Scientific EffectAbrasion: Abrasion

Implementation Method 4

high-k dielectric layer

Methodology Applied
Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Data Source

PatentUS11769690B2Semiconductor device and method of fabricating the same
Publication Date: 2023.09.26 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11769690B2 patent drawing
  • US11769690B2 patent drawing
  • US11769690B2 patent drawing

AI summary

A device includes a substrate, a first metal feature over the substrate, first and second spacers, a first dielectric layer, and a second metal feature. The first and second spacers are on opposite sidewalls of the conductive feature, respectively. The first dielectric layer is in contact with the first spacer, in which a top surface of the protection layer is higher than a top surface of the first spacer. The second metal feature is electrically connected to the first metal structure and in contact with a top surface and a sidewall of the protection layer.