3D CMOS Gate Contacts Across Fin and Nanosheet Crystal Planes
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down integrated circuits (ICs) while maintaining functional density and efficiency, particularly in designing and manufacturing three-dimensional structures like fin field-effect transistors (FinFETs).
Innovation Solution
The manufacturing process involves forming stacked semiconductor layers with alternating layers of channel material and sacrificial material, followed by patterning to create nanosheets and semiconductor fins. Gate structures are then formed to contact these features, optimizing contact areas along different crystallographic surfaces to enhance charge transport.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If geometry size is decreased to increase functional density, then production efficiency and cost are improved, but manufacturing precision and fabrication challenges worsen
Solution Approach 1:
The patent transitions from planar 2D transistors to three-dimensional FinFET structures, utilizing vertical channel regions that extend upward from the substrate. This dimensional change allows continued scaling of functional density while maintaining manufacturable geometry sizes, as the vertical fins provide increased channel area without proportionally reducing the lithographic footprint.
Solution Approach 2:
The channel region is segmented into multiple vertical fin structures rather than a single planar channel. Each fin acts as an independent channel segment, allowing the total channel area to be increased through multiplication of segments rather than continuous scaling of individual feature sizes, thereby improving manufacturing precision requirements.
2Reliability
If three-dimensional structures like FinFETs are designed to maintain functional density during scaling, then device performance is improved, but fabrication complexity increases
Solution Approach 1:
The FinFET structure serves multiple functions simultaneously: the vertical fins provide increased channel area for higher drive current, the gate structure wraps around the fins for improved electrostatic control, and the overall architecture enables continued scaling. This multi-functionality in a single structure reduces the need for additional complex fabrication steps compared to alternative 3D approaches.
Data Source
AI summary
A manufacturing method of a complementary metal-oxide-semiconductor device includes forming semiconductor fins over a semiconductor substrate; forming nanosheets over the semiconductor substrate; forming a gate structure contacting the semiconductor fins and the nanosheets, where a contact area of the gate structure with the semiconductor fins extends mostly along a (110) crystallographic surface of a semiconductor material of the semiconductor fins, and a contact area of the gate structure with the nanosheets extends mostly along a (100) crystallographic surface of a semiconductor material of the nanosheets.