CMOS Gate Anti-Type Doping for Hump-Effect Voltage Reference Stability
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Solution Overview
Problem
Ultra-low-power CMOS voltage reference circuits face accuracy and precision issues due to the 'hump effect' caused by divot features in shallow trench isolation structures, leading to variations in threshold voltage and reduced performance.
Innovation Solution
Incorporating a gate anti-type doped region, such as P+ regions, in the normal gate transistor device to minimize leakage current and reduce the impact of divot features, thereby improving the accuracy and stability of the voltage reference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a normal gate transistor device is used without anti-type doped regions, then the device structure is simpler and manufacturing is easier, but leakage current increases and voltage reference accuracy deteriorates due to the hump effect from divot features
Solution Approach 1:
The patent applies local quality by introducing P+ anti-type doped regions specifically at the gate edges where divot features cause leakage current, while leaving the rest of the gate structure unchanged. This targeted approach addresses the localized hump effect problem without requiring complete redesign of the entire gate structure, thus improving voltage reference accuracy while minimizing added complexity
Solution Approach 2:
The patent converts the harmful divot feature effect into a benefit by using the same divot structure to define the location of anti-type doped regions. The P+ regions are positioned to align with the divot features, transforming the leakage-inducing divots into localized zones where anti-type doping effectively suppresses the hump effect and improves threshold voltage stability
2Reliability
If gate anti-type doped regions are added to minimize leakage current, then voltage reference accuracy and stability improve, but manufacturing process complexity and cost increase
Solution Approach 1:
The patent merges the formation of anti-type doped regions with existing source/drain doping processes by using the same photomask alignment and implantation steps. The P+ regions are created during the same fabrication sequence as the N+ source and drain regions, consolidating multiple doping operations into a unified process flow, thereby improving reliability while minimizing the impact on manufacturing ease
Solution Approach 2:
The patent employs self-aligned fabrication where the anti-type doped regions are automatically positioned relative to the gate structure using the gate itself as the alignment reference. This self-service approach eliminates the need for additional complex alignment steps and photomasks, allowing the structure to define its own doping regions, thus improving voltage reference stability without significantly complicating the manufacturing process
3Manufacturing precision
If P+ regions are implanted in the N+ gate structure, then the hump effect is reduced and threshold voltage variations decrease, but the doping process complexity and precision requirements increase
Solution Approach 1:
The patent achieves equipotentiality by ensuring that the P+ anti-type doped regions are positioned at the same potential as the N+ gate structure during doping, using identical photomask alignment and implantation energy settings. This approach ensures uniform doping conditions across different regions, improving threshold voltage control while avoiding the need for separate complex doping processes with different parameters
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of gate anti-type doped regions enhances the accuracy and precision of the voltage reference by reducing the hump effect, resulting in a more stable and precise reference voltage generation.
Implementation Method 1
Incorporating a gate anti-type doped region, such as P+ regions, in the normal gate transistor device to minimize leakage current and reduce the impact of divot features
Data Source
AI summary
Some embodiments relate to an integrated circuit (IC) device that includes a substrate including a P-well region and a dielectric structure. The dielectric structure is disposed at a surface of the substrate, extends downward into the substrate, and is located at a lateral perimeter of the P-well region. The IC device further includes a dielectric layer disposed over the P-well region and extends laterally over the dielectric structure. The IC device also includes an N+ gate structure disposed over the dielectric layer and includes at least one P+ region located over the P-well region of the substrate and the dielectric structure.