CMOS Gate Work Function Doping for Uniform Etching
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Solution Overview
Problem
The challenge in semiconductor manufacturing is the uneven etching of PMOS and NMOS transistors due to different work function layer thicknesses, leading to degraded yield and reliability of semiconductor devices.
Innovation Solution
A semiconductor structure and preparation method that involves doping treatments to adjust the work function layers of PMOS and NMOS regions, ensuring the first and second work function layers are formed based on initial work function layers, with dopant ions like aluminum and lanthanum ions, to achieve consistent gate heights and simplify the etching process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If different thicknesses of work function layers are used for PMOS and NMOS transistors to achieve respective threshold voltages, then the transistors can reach their expected threshold voltages, but uneven etching occurs in subsequent etching processes which degrades yield and reliability
Solution Approach 1:
The patent changes the material composition parameter of the work function layer by doping it with specific dopants (aluminum, cobalt, nickel, ruthenium, rhodium, palladium, rhenium, iridium, or platinum ions) to adjust the work function value. This allows achieving the required threshold voltages for both PMOS and NMOS transistors while maintaining uniform layer thickness, thereby resolving the contradiction between threshold voltage control and etching uniformity
Solution Approach 2:
The patent applies different doping treatments to the work function layer in different regions (PMOS region versus NMOS region) to create local variations in work function value. By doping the work function layer with appropriate dopants in each region, the patent achieves region-specific threshold voltage control while maintaining overall etching uniformity across the substrate
2Measurement precision
If the gate-first process is used to control threshold voltage through work function layer thickness adjustment, then transistor threshold voltages can be controlled, but the process complexity increases and yield decreases due to uneven etching
Solution Approach 1:
Instead of controlling threshold voltage through work function layer thickness adjustment, the patent changes the work function value by doping the work function layer with specific dopants. This material composition change allows threshold voltage control without requiring different thicknesses, thereby simplifying the overall process and reducing complexity while maintaining yield
3Reliability
If work function layers with different thicknesses are deposited to achieve different work functions, then PMOS and NMOS transistors can reach their expected threshold voltages, but the etching process becomes uneven which degrades yield and reliability
Solution Approach 1:
The patent changes the chemical composition parameter of the work function layer through doping with specific dopant ions, allowing achievement of different work function values while maintaining uniform thickness. This resolves the contradiction between transistor performance (requiring different work functions) and manufacturing yield (requiring uniform etching)
Solution Approach 2:
The patent performs doping treatment on the work function layer before the etching process to establish the required work function values in advance. This preliminary action ensures that both PMOS and NMOS transistors achieve their expected threshold voltages while maintaining uniform layer thickness that enables uniform etching, thereby improving yield and reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the process, reduces the height difference between PMOS and NMOS regions, stabilizes threshold voltages, and improves the yield and reliability of semiconductor devices by ensuring consistent etching and easier work function adjustments.
Implementation Method 1
performing a first doping treatment on an initial work function layer of a PMOS region and adjusting a work function value of the initial work function layer of the PMOS region
Data Source
AI summary
A semiconductor structure and a preparation method therefor are provided. The semiconductor structure includes: a substrate, a gate dielectric layer, a first gate in a PMOS region, and a second gate in an NMOS region. The substrate includes a PMOS region and an NMOS region; the gate dielectric layer is located on the substrate of the PMOS region and of the NMOS region. The first gate includes a first work function layer and a first gate electrode layer that are stacked. The first work function layer is formed based on a first doping treatment of an initial work function layer. The second gate includes a second work function layer and a second gate electrode layer that are stacked. The semiconductor structure and the preparing method provided in the present disclosure can alleviate uneven etching of a PMOS transistor and an NMOS transistor and improve the yield and reliability of semiconductor devices.