CMOS Gate Electrode Insulation Layout to Suppress Dopant Diffusion
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Solution Overview
Problem
Very low voltage transistors in semiconductor devices deteriorate in characteristics during manufacturing due to gate electrode configuration, leading to increased resistance and reduced performance.
Innovation Solution
The semiconductor device is configured with PMOS and NMOS transistors having distinct gate insulating layer thicknesses, with the PMOS transistor's insulating layer being thicker than the NMOS transistor's to prevent interdiffusion of dopants and maintain low resistance, thereby improving transistor quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a gate electrode configuration is used in very low voltage transistors, then high-speed operation is achieved, but characteristics deteriorate during manufacturing due to increased resistance
Solution Approach 1:
The patent applies different insulating layer thicknesses to different transistor types (PMOS vs NMOS) within the same device. The PMOS transistor has a thicker first insulating layer while the NMOS transistor has a thinner second insulating layer, creating local quality differences that prevent dopant interdiffusion and maintain low resistance in both transistor types, thereby resolving the contradiction between high-speed operation and manufacturing reliability
Solution Approach 2:
The patent changes the physical parameter of insulating layer thickness to prevent dopant diffusion. By making the first insulating layer thickness greater than the second insulating layer thickness, the patent modifies the structural parameters to suppress harmful dopant interdiffusion during manufacturing, maintaining low resistance and improving transistor characteristics while preserving high-speed operation capabilities
2Ease of manufacture
If the gate insulating layer thickness is made uniform, then manufacturing is simplified, but dopant interdiffusion occurs between PMOS and NMOS transistors
Solution Approach 1:
The patent implements local quality by assigning different insulating layer thicknesses to different transistor regions. The first insulating layer over the PMOS transistor is thicker than the second insulating layer over the NMOS transistor, creating region-specific properties that prevent dopant interdiffusion while maintaining manufacturing feasibility through a systematic thickness differentiation approach
3Reliability
If the insulating layer is made thinner to reduce resistance, then conductivity improves, but dopant diffusion increases between transistor types
Solution Approach 1:
The patent applies local quality by making the second insulating layer (NMOS) thinner than the first insulating layer (PMOS). This localized thickness reduction in the NMOS region maintains low resistance and good conductivity while the thicker first insulating layer in the PMOS region prevents dopant diffusion, thereby simultaneously achieving good electrical conductivity and stable dopant distribution through region-specific optimization
Solution Approach 2:
The patent changes the insulating layer thickness parameter differently for PMOS and NMOS transistors. By setting the first insulating layer thickness to be greater than the second insulating layer thickness, the patent optimizes the thickness parameter to balance conductivity requirements (thinner layer) with dopant diffusion prevention (thicker layer) across different transistor types
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The configuration suppresses dopant diffusion, maintaining low resistance and enhancing the performance and quality of the PMOS and NMOS transistors, resulting in a high-quality semiconductor device.
Implementation Method 1
A film thickness of the first insulating layer is thicker than a film thickness of the second insulating layer to suppress diffusion of a dopant from the first semiconductor layer into the first conductive layer
Data Source
AI summary
According to one embodiment, a semiconductor device includes: a first well region of N-type and a second well region of P-type; a PMOS transistor provided in the first well region; and an NMOS transistor provided in the second well region. The PMOS transistor includes a first gate insulating layer and a first gate electrode. The NMOS transistor includes a second gate insulating layer and a second gate electrode. The first gate electrode includes a first semiconductor layer of P-type, a first insulating layer, and a first conductive layer. The second gate electrode includes a second semiconductor layer of N-type, a second insulating layer, and a second conductive layer. A film thickness of the first insulating layer is thicker than a film thickness of the second insulating layer.