CMOS Power Switching Circuit With Zener-Free Gate Level Shifting
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Solution Overview
Problem
Conventional power switching circuits in DC-DC converters require large high voltage driver transistors and Zener diodes, increasing the size and cost, and limiting the adjustability of the minimum output voltage.
Innovation Solution
A power switching circuit in CMOS technology using a pair of driver MOS transistors connected in series with a non-linear component and resistors to achieve level-shifting without Zener diodes, allowing operation beyond the maximum gate-source voltage of the power MOS transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional level shifters with large high voltage driver transistors and Zener diodes are used, then the power MOS transistor can be operated at high supply voltage, but the circuit size and cost increase
Solution Approach 1:
The patent changes the voltage level parameters by using a voltage divider network (R1, R2, R3) to step down the high supply voltage to a level suitable for driving the CMOS inverter. This allows the power MOS transistor to operate at high voltage while the control circuitry operates at lower voltage, eliminating the need for large high voltage driver transistors and Zener diodes
Solution Approach 2:
The patent introduces an intermediary voltage division stage between the high voltage power supply and the low voltage CMOS inverter. The resistors R1, R2, and R3 form a voltage divider that mediates the voltage level transition, allowing the gate voltage to be appropriately scaled without requiring special high voltage components
2Reliability
If conventional level shifters with Zener diodes are used, then the gate-source voltage can be protected, but the minimum output voltage adjustability is limited
Solution Approach 1:
The patent makes the voltage division ratio dynamic and adjustable by allowing different resistor values in the voltage divider network. This enables the minimum output voltage to be adapted to different application requirements while still providing adequate gate voltage protection through the controlled voltage division
Solution Approach 2:
By changing the resistor values (R1, R2, R3) in the voltage divider, the patent can adjust the voltage transformation ratio to match different output voltage requirements. This provides flexibility in setting the minimum output voltage without being constrained by fixed Zener diode voltage values
3Power
If large high voltage driver transistors are used, then the power MOS transistor can be driven at high voltage, but the integration density decreases
Solution Approach 1:
The patent segments the voltage drive function into two separate stages: a high voltage power MOS transistor for power switching and a low voltage CMOS inverter for control logic. The voltage divider network bridges these two segments, allowing each transistor to be optimized for its specific voltage range and minimizing the area required for driver transistors
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables fast switching and increased efficiency with reduced circuit complexity and cost, while allowing adjustable gate voltage levels for optimal performance.
Implementation Method 1
The gates of the driver MOS transistors are each connected to the higher voltage supply rail through a parallel connection of a first resistor on the one hand, and through a second resistor connected in series with a non-linear component on the other hand. The resistance value of the second resistor is substantially smaller than the resistance value of the first resistor.
Implementation Method 2
The non-linear component connected in series with a relatively small resistor acts effectively as a non-linear resistor in combination with the relatively large parallel-connected resistor to reduce the gate voltage at the corresponding driver MOS transistor.
Data Source
AI summary
A power switching circuit in CMOS technology has a power MOS transistor and a driver stage. The power MOS transistor is operated at a higher supply voltage in excess of its maximum allowable gate-source voltage; and the driver stage of the level shifter is operated at a lower supply voltage substantially lower than the supply voltage for the power MOS transistor. The driver stage includes a pair of driver MOS transistors coupled in series between a higher supply voltage rail and a reference potential rail, and at an interconnection node coupled to the gate of the power MOS transistor. The gates of the driver MOS transistors are AC-coupled to drive signals of mutually opposite phase; and the gates of the driver MOS transistors are each connected to the higher voltage supply rail through a respective parallel connection of a first resistor and a second resistor connected in series with a non-linear component. The resistance value of the second resistor is substantially smaller than the resistance value of the first resistor.