CMOS Gate Electrode Formation via Placeholder Replacement

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Solution Overview

Problem

The challenge in fabricating advanced integrated circuits is the complexity in forming gate electrode structures with high-k dielectric materials, which often results in plasma-induced damage and increased process variability due to the need for sophisticated lithography and plasma-assisted etch techniques, leading to inferior performance and yield loss.

Innovation Solution

The approach involves forming gate electrode structures using a high-k dielectric material combined with a metal-containing electrode material, where a placeholder material is replaced after high-temperature treatments, and an intermediate liner is used to avoid plasma-assisted etch processes, allowing for early lithography and reduced process complexity, enabling superior controllability and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If sophisticated lithography and plasma-assisted etch techniques are used to form gate electrode structures with high-k dielectric materials, then the precision and controllability of gate formation is improved, but plasma-induced damage and process variability increase

Engineering Contradiction:
Improvegate formation precisionVSAvoidprocess reliability
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent introduces a placeholder material (such as silicon oxide or silicon nitride) as an intermediary layer between the high-k dielectric material and the final metal gate electrode. This placeholder material serves as a protective intermediary that prevents direct plasma exposure to the high-k dielectric interface, thereby reducing plasma-induced damage while still allowing precise gate formation through subsequent metal deposition processes

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent performs preliminary formation of the gate electrode structure using the placeholder material before final metal gate deposition. The placeholder material is formed early in the process sequence, allowing subsequent high-temperature treatments and metal deposition to proceed without risking plasma damage to the high-k dielectric interface. This preliminary structure is later replaced or modified to achieve the final metal gate configuration

Inventive Principle:
Principle #10Preliminary action

2Reliability

If placeholder material is replaced after high-temperature treatments, then plasma-induced damage is reduced, but additional process steps are required

Engineering Contradiction:
Improveprocess reliabilityVSAvoidprocess complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines multiple functions into the placeholder material layer: it serves as a plasma protection layer during high-temperature treatments, as a temporary structural support during metal gate deposition, and as a sacrificial layer that is later removed to allow direct metal contact with the high-k dielectric. By merging these functions into a single material layer, the patent reduces overall process complexity despite adding the initial placeholder formation step

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If intermediate liner is used to avoid plasma-assisted etch processes, then plasma-induced damage is reduced, but work function adjustment becomes more challenging

Engineering Contradiction:
Improveinterface integrityVSAvoidwork function adjustment
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent adjusts the work function of the metal gate electrode by changing the material composition and thickness parameters of the metal layer deposited over the placeholder material. By controlling the metal deposition parameters (such as deposition rate, temperature, and layer thickness), the work function can be precisely tuned to achieve desired transistor threshold voltages, even with the intermediate placeholder material present

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method reduces plasma-induced damage and process complexity, enhancing the controllability and reliability of gate electrode structures, allowing for accurate work function adjustment without additional lithography steps, thereby improving the performance and yield of semiconductor devices.

Implementation Method 1

the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 2

removing material of the placeholder material in the first and second gate electrode structures so as to expose the metal-containing electrode material or the high-k dielectric material

Methodology Applied
Scientific EffectEtching:

Implementation Method 3

a placeholder material is replaced after high-temperature treatments

Methodology Applied
Scientific EffectThermal treatment: Heat Treatment

Data Source

PatentUS8367495B2Method for forming CMOS transistors having metal-containing gate electrodes formed on a high-K gate dielectric material
Publication Date: 2013.02.05 GLOBALFOUNDRIES US INC
  • US8367495B2 patent drawing
  • US8367495B2 patent drawing
  • US8367495B2 patent drawing

AI summary

During the formation of sophisticated gate electrode structures, a replacement gate approach may be applied in which plasma assisted etch processes may be avoided. To this end, one of the gate electrode structures may receive an intermediate etch stop liner, which may allow the replacement of the placeholder material and the adjustment of the work function in a later manufacturing stage. The intermediate etch stop liner may not negatively affect the gate patterning sequence.