CMOS Gate Stack Dipole Engineering for Threshold Voltage Control
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Solution Overview
Problem
Existing semiconductor devices face challenges in optimizing the threshold voltage of N-channel and P-channel MOSFETs in CMOS integrated circuits due to limitations in gate dielectric layer thickness and dopant diffusion, leading to increased leakage current and reduced drive current.
Innovation Solution
A gate stack structure is developed with a high-k dielectric layer, a metal layer, and a capping layer, where chemical species form dipoles at the interface between the metal and capping layers, allowing independent control of threshold voltages for NMOS and PMOS by using arsenic and germanium, respectively, to reduce threshold voltages and enhance drive current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the thickness of the silicon oxide gate dielectric layer is physically reduced to enhance gate voltage control power and increase drive current, then the drive current is improved, but the off-state characteristic degrades due to increased leakage current caused by direct tunneling
Solution Approach 1:
The patent changes the dielectric constant parameter of the gate dielectric layer from conventional silicon oxide (k≈3.9) to high-k dielectric materials (k>10), enabling thicker physical thickness while maintaining equivalent electrical thickness, thus reducing direct tunneling leakage while preserving gate control
Solution Approach 2:
The patent employs composite gate structures combining high-k dielectric layers with metal gate electrodes, creating a composite material system that simultaneously achieves low leakage current through high-k dielectric and high drive current through metal gate conductivity
2Manufacturing precision
If doped silicon is used to implement gate electrodes of NMOS and PMOS during CMOS integrated circuit process to optimize threshold voltage, then the threshold voltage is optimized, but the drive current is reduced by gate depletion
Solution Approach 1:
The patent substitutes doped silicon gate electrodes with metal gate electrodes, replacing the mechanical/diffusion-based threshold control mechanism with an electric field-based metal gate control, eliminating boron out-diffusion and gate depletion effects
Solution Approach 2:
The patent introduces high-k dielectric layers as intermediary materials between the substrate and metal gate electrodes, mediating the electrical field distribution to enable independent threshold voltage control without compromising drive current
3Manufacturing precision
If boron is implanted into the P+-doped silicon of PMOS to optimize threshold voltage, then the threshold voltage is optimized, but the boron may be out-diffused through subsequent thermal process and the gate depletion of PMOS may further increase by 10%, compared with NMOS
Solution Approach 1:
The patent replaces doped silicon gate electrodes with metal gate electrodes, eliminating the need for boron implantation and subsequent thermal diffusion processes, thereby preventing boron out-diffusion and associated threshold voltage instability
Solution Approach 2:
The patent extracts and removes the problematic boron doping step from the PMOS fabrication process by using metal gates that do not require dopant implantation, eliminating the source of out-diffusion issues
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces threshold voltages and improves drive current by inducing electronic polarization and decreasing energy band gaps, enabling better control and optimization of NMOS and PMOS performance during CMOS integration.
Implementation Method 1
a plurality of dipole forming chemical element concentrated at the interface between the metal layer and the capping layer, wherein the chemical species form dipoles
Implementation Method 2
gate dielectric layer formed over a substrate and a gate electrode formed over a gate dielectric layer
Data Source
AI summary
A semiconductor device includes a gate dielectric layer over a substrate, a metal layer over the gate dielectric layer, a capping layer over the metal layer, wherein the capping layer includes a plurality of dipole forming elements concentrated at the interface between the metal layer and the capping layer.