CMOS Gate Stack Using Midgap Metal for Process Simplification
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Solution Overview
Problem
Conventional CMOS gate stack processes are complex and inefficient due to asymmetry in NMOS and PMOS processing steps, leading to increased complexity, sensitivity to variations, and higher failure rates, particularly in low threshold voltage device manufacturing.
Innovation Solution
The introduction of a deeply depleted channel (DDC) transistor architecture that uses similar metal gate processes for both PMOS and NMOS transistors, eliminating the need for SiGe channels and simplifying the gate stack formation by using a single, close to midgap workfunction metal, thereby reducing process complexity and improving yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If asymmetric processing steps are used for NMOS and PMOS transistors to achieve different threshold voltages, then device performance is improved, but process complexity and sensitivity to variations increase
Solution Approach 1:
The patent changes the material parameter (workfunction) of the metal gate to achieve different threshold voltages for NMOS and PMOS transistors. By selecting metals with appropriate workfunctions (e.g., tungsten for NMOS, titanium nitride for PMOS), the invention enables asymmetric electrical characteristics using a symmetric processing approach, thereby improving device performance without increasing process complexity
Solution Approach 2:
The patent employs a universal metal gate deposition process that serves multiple functions: it forms the gate electrode, sets the threshold voltage through workfunction selection, and provides thermal stability. This multi-functional approach eliminates the need for separate processing steps for NMOS and PMOS, reducing overall process complexity while maintaining device performance
2Manufacturing precision
If conventional metal gate processes are used for low threshold voltage devices, then threshold voltage control is improved, but device failure rates increase due to sensitivity to variations
Solution Approach 1:
The patent applies local quality by using different metal materials with specific workfunctions in different device regions. NMOS devices use metals with lower workfunctions (e.g., tungsten at 4.5 eV) to achieve low threshold voltages, while PMOS devices use metals with higher workfunctions (e.g., titanium nitride at 4.7 eV). This localized material selection enables precise threshold voltage control for each device type while maintaining robustness against process variations
Solution Approach 2:
The patent employs composite gate stack structures combining metal gates with high-k dielectric materials (e.g., hafnium oxide). This composite approach provides both excellent threshold voltage control through workfunction engineering and improved reliability by reducing sensitivity to interface states and process variations, thereby lowering device failure rates
3Manufacturing precision
If dual metal gate stacks are used for PMOS and NMOS transistors, then threshold voltage differentiation is improved, but manufacturing efficiency decreases
Solution Approach 1:
The patent segments the metal gate deposition process into separate steps for NMOS and PMOS regions using selective epitaxial growth or selective chemical vapor deposition. This segmentation allows different metal materials to be deposited in different device regions without requiring complete removal and redeposition, thereby achieving threshold voltage differentiation while maintaining manufacturing efficiency
Solution Approach 2:
The patent performs preliminary action by pre-defining the metal gate material selection based on the desired threshold voltage characteristics before actual device fabrication. Workfunction calculations and material selection are completed in advance, allowing for optimized deposition parameters and reduced process iterations, thus improving manufacturing efficiency while maintaining precise threshold voltage differentiation
Data Source
AI summary
A semiconductor device includes a substrate having a semiconducting surface having formed therein a first active region and a second active region, where the first active region consists of a substantially undoped layer at the surface and a highly doped screening layer of a first conductivity type beneath the first substantially undoped layer, and the second active region consists of a second substantially undoped layer at the surface and a second highly doped screening layer of a second conductivity type beneath the second substantially undoped layer. The semiconductor device also includes a gate stack formed in each of the first active region and the second active region consists of at least one gate dielectric layer and a layer of a metal, where the metal has a workfunction that is substantially midgap with respect to the semiconducting surface.