CMOS FinFET Gate Stack for Threshold Voltage Tuning
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Solution Overview
Problem
As CMOS technology advances, scaling down n-type and p-type field effect transistors on semiconductor devices poses challenges in achieving desired threshold voltages and efficient integration of complex circuits.
Innovation Solution
The formation of semiconductor devices involves creating n-channel and p-channel transistors or nanowires using materials like silicon and silicon germanium, with controlled germanium concentration and rare earth compound-doped cap layers to tune threshold voltages, and the use of high-k dielectric materials and metal gate electrodes to enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor size is scaled down to increase integration density, then circuit complexity and integration capacity improve, but achieving desired threshold voltages becomes more difficult
Solution Approach 1:
The patent applies local quality by using different semiconductor materials (silicon, silicon germanium with varying germanium concentrations) for different transistor regions. Specifically, first transistors use silicon channels while second transistors use silicon germanium channels with controlled germanium concentrations (1-50%), allowing each region to have optimized electrical properties for its specific function, thus maintaining threshold voltage control despite overall device scaling.
Solution Approach 2:
The patent employs parameter changes by varying the germanium concentration in silicon germanium channels across different transistor regions. By adjusting the germanium content parameter (from 1% to 50%), the patent tunes the threshold voltage and carrier mobility to achieve desired electrical characteristics in scaled-down devices without compromising integration density.
2Manufacturing precision
If heterogeneous materials are used to tune threshold voltages, then threshold voltage precision improves, but device structure and material integration become more complex
Solution Approach 1:
The patent utilizes composite materials by combining silicon and silicon germanium in a unified semiconductor structure. The silicon germanium channels with controlled germanium concentrations (1-50%) are integrated alongside silicon-based structures, creating a composite material system that enables precise threshold voltage tuning while maintaining compatibility with existing semiconductor manufacturing processes.
Solution Approach 2:
The patent applies local quality by implementing material variations only where needed - specifically in the channel regions of second transistors - while keeping first transistors as conventional silicon devices. This localized approach to material heterogeneity achieves threshold voltage control without requiring complex heterogeneous integration across the entire device structure.
Data Source
AI summary
A semiconductor device includes first and second fins, first and second hafnium oxide layers, first and second cap layers, and first and second metal gate electrodes. The first and second fins protrude above a substrate and respectively have an n-channel region and a p-channel region. The first and second hafnium oxide layers wrap around the n-channel region and the p-channel region, respectively. The first and second cap layers wrap around the first and second annular hafnium oxide layers, respectively. The first and second cap layers are made of a same material that is lanthanum oxide, yttrium oxide, or strontium oxide. The first and second metal gate electrodes wrap around the first and second cap layers, respectively. The first and second metal gate electrodes have a same metal composition. The first and second gate dielectrics have a same dielectric composition.