CMOS Gate Stack Tunable Threshold Voltage via Block Mask
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Solution Overview
Problem
Existing methods for controlling threshold voltage in CMOS structures, particularly those using high k gate dielectrics, face issues such as non-ideal threshold voltage, increased Gate-Induced Drain Leakage (GIDL) current, and dimensional deviations due to residual traces from threshold voltage adjusting layers and wet etching processes.
Innovation Solution
The method involves selective placement of threshold voltage adjusting materials using block masks before deposition, allowing for patterned threshold voltage adjusting materials on semiconductor substrates, enabling the use of a single conductive material and high k gate dielectric for both nFET and pFET devices, and forming gate stacks with tunable threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If threshold voltage adjusting layers are deposited as blanket layers and patterned by wet etching, then threshold voltage control is achieved, but dimensional accuracy deteriorates due to undercutting and residual traces
Solution Approach 1:
The patent applies preliminary action by forming block masks before depositing threshold voltage adjusting layers. The block masks define the precise pattern areas where adjusting layers should be deposited, preventing unwanted deposition in non-patterned regions and eliminating the need for subsequent wet etching that causes undercutting. This preliminary patterning step ensures dimensional accuracy is maintained throughout the process.
Solution Approach 2:
The patent extracts the problematic wet etching step from the process flow by using block masks to define patterns before deposition. The block masks serve as physical barriers that prevent the need for chemical etching, thereby removing the source of undercutting and residual traces that compromise gate stack dimensional accuracy.
2Measurement precision
If different conductivity type transistors are formed on gate oxides with different thicknesses, then threshold voltage control is achieved, but device complexity increases
Solution Approach 1:
The patent applies local quality by using block masks to selectively deposit threshold voltage adjusting layers only in specific patterned regions. This allows different threshold voltage adjustments to be applied locally to different transistor regions (nFET and pFET) while maintaining a uniform gate oxide thickness across the entire substrate, thereby reducing device complexity compared to varying gate oxide thicknesses.
Solution Approach 2:
The patent changes the parameter being adjusted from gate oxide thickness to threshold voltage adjusting layer composition and thickness. By keeping the gate oxide thickness uniform and introducing adjustable layers with different properties (n-type or p-type doping) only where needed through block mask patterning, the patent achieves threshold voltage control without the complexity of varying fundamental device structure parameters.
3Object-generated harmful factors
If high k dielectrics are used as gate insulating film, then gate leakage current is reduced, but threshold voltage control becomes non-ideal
Solution Approach 1:
The patent introduces threshold voltage adjusting layers as intermediary elements between the high k gate dielectric and the channel region. These adjusting layers serve as mediators that provide the necessary threshold voltage control that the high k dielectric alone cannot achieve, while the high k dielectric continues to provide its primary function of reducing gate leakage current. The block mask process ensures these intermediary layers are precisely placed only where needed.
Data Source
AI summary
Methods of forming complementary metal oxide semiconductor (CMOS) structures with tunable threshold voltages are provided. The methods disclose a technique of obtaining selective placement of threshold voltage adjusting materials on a semiconductor substrate by using a block mask prior to deposition of the threshold voltage adjusting materials. The block mask is subsequently removed to obtain a patterned threshold voltage adjusting material on the semiconductor substrate. The methods are material independent and can be used in sequence for both nFET threshold voltage adjusting materials and pFET threshold voltage adjusting materials.