CMOS Gate Multi-Input Switching Delay via Parallel Current Models
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Solution Overview
Problem
Existing IC design tools struggle to accurately calculate multi-input switching (MIS) delay of CMOS logic gates, relying on grossly inaccurate single derating factors or impractical table-based methods, which affects the accuracy of static timing analysis (STA) and timing requirements in integrated circuit design.
Innovation Solution
The approach involves determining MIS pin sets, constructing equivalent parallel current source models, and simulating these models to capture the output waveform, thereby accurately calculating the minimum switching delay of CMOS logic gates without explicit library characterization, using existing library data and non-linear delay models to align input waveforms for precise delay determination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If single derating factors are used to calculate MIS delay, then calculation simplicity is maintained, but accuracy of timing analysis deteriorates
Solution Approach 1:
The patent transforms the delay calculation from using fixed single derating factors to using dynamically calculated derating factors based on the number of simultaneously switching inputs. The derating factor is computed as (N-1)/N where N is the number of switching inputs, allowing the parameter to adapt to different switching scenarios and improve accuracy while maintaining computational efficiency.
Solution Approach 2:
The patent extracts the multi-input switching behavior from the traditional single-input delay model by identifying and separating the derating component. This extracted derating factor is then applied specifically to account for MIS effects, allowing the base delay model to remain simple while adding accuracy only where needed for multi-input scenarios.
2Measurement precision
If table-based methods are used to characterize MIS delay, then accuracy can be improved, but device complexity and runtime overhead increase
Solution Approach 1:
The patent segments the MIS delay calculation into distinct components: base delay from standard library characterization and an additional derating component. This segmentation allows the use of existing simple library models while adding a separate calculated component for MIS effects, avoiding the need for complex pre-characterized tables.
Solution Approach 2:
The patent enables the timing analysis tool to self-correct for MIS effects by automatically calculating derating factors during analysis based on the switching behavior of inputs. This eliminates the need for external pre-characterization tables, as the system generates its own correction factors dynamically during the timing analysis process.
3Measurement precision
If iterative analyses are performed to achieve SPICE-level accuracy, then measurement precision improves, but productivity and runtime efficiency deteriorate
Solution Approach 1:
The patent performs preliminary identification of simultaneously switching inputs and calculates the appropriate derating factor before the main timing analysis. This preliminary action prepares the corrected delay values in advance, allowing the subsequent timing analysis to proceed efficiently without iterative SPICE-level simulations, thus achieving high accuracy with single-pass computation.
Data Source
AI summary
Techniques and systems for determining an output waveform at an output of a complementary metal-oxide-semiconductor (CMOS) logic gate are described. Some embodiments can identify at least one set of inputs of the CMOS logic gate that, when switched together, causes multiple transistors coupled in parallel to simultaneously turn-on and drive the output of the CMOS logic gate. Next, the embodiments can determine a set of current source models that are coupled in parallel to model the CMOS logic gate when the set of inputs of the CMOS logic gate are switched together. The embodiments can then simulate the set of current source models together to determine the output waveform at the output of the CMOS logic gate when the set of inputs of the CMOS logic gate are switched together.