CMOS Gate Stack Scheme for More Threshold Voltages
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Solution Overview
Problem
Current CMOS transistor technologies face challenges in efficiently modulating threshold voltage across multiple devices on a common substrate with a reduced number of fabrication steps, limiting the variety of threshold voltages achievable.
Innovation Solution
The implementation of a multiple threshold voltage scheme using a semiconductor structure with a common substrate, featuring multiple field effect transistor (FET) gates with different threshold voltages achieved by employing a combination of barrier layers and work function metals, where the addition of a second work function metal allows for doubling the number of threshold voltages without increasing the number of patterning steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single work function metal is used in the gate stack, then the fabrication process is simple, but the number of different threshold voltages achievable is limited
Solution Approach 1:
The gate stack is segmented into multiple functional layers: barrier layers with different thicknesses (first barrier layer, second barrier layer) and multiple work function metal layers (first work function metal, second work function metal). Each layer can be independently configured to achieve different threshold voltages, allowing 4 different threshold voltages from a single gate stack structure without requiring additional patterning steps.
Solution Approach 2:
The gate stack employs composite material structure combining different barrier layer materials (e.g., TiN, TaN) with different work function metal materials (e.g., Ti, W, Mo). The combination of these materials with varying thicknesses creates multiple threshold voltage states, enabling versatile device characteristics while maintaining fabrication simplicity.
2Adaptability or versatility
If multiple barrier layers with different thicknesses are used to achieve different threshold voltages, then threshold voltage variety increases, but the number of fabrication steps increases proportionally
Solution Approach 1:
Multiple threshold voltage control mechanisms are merged into a single gate stack structure. The barrier layers and work function metals are combined in a unified stack where the first barrier layer with first work function metal provides one threshold voltage, and the second barrier layer with second work function metal provides another threshold voltage, all within the same fabrication sequence without additional patterning steps.
Solution Approach 2:
The patent transitions from controlling threshold voltage through a single parameter (barrier layer thickness) to a multi-dimensional approach using both barrier layer thickness and work function metal type/composition. This adds another dimension of control, allowing 4 different threshold voltages to be achieved by varying combinations of two barrier layers and two work function metals, doubling the achievable threshold voltage variety without doubling the fabrication steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient modulation of threshold voltages in adjacent devices with a reduced number of fabrication steps, providing multiple threshold voltages through the use of different barrier layers and work function metals, thereby enhancing power efficiency and flexibility in circuit design.
Implementation Method 1
a high-κ dielectric layer
Implementation Method 2
Threshold voltage can be tuned by controlling the material composition of a transistor, for example, by adjusting the compositions of a barrier layer and of a work function metal layer
Data Source
AI summary
A semiconductor structure includes a common semiconductor substrate; a first field effect transistor (FET) gate formed on the substrate, which has a first threshold voltage and comprises a first work function metal and a first barrier layer, and a second FET gate formed on the substrate, which has a second threshold voltage and comprises the first work function metal, the first barrier layer, and a second work function metal.