CMOS Gate Work Function Optimization via Segmented Metal Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current CMOS semiconductor device manufacturing faces challenges in scaling and optimizing gate structures for improved performance, particularly in achieving suitable work functions for n-type and p-type semiconductor devices while maintaining equivalent field effect performance.
Innovation Solution
The method involves forming gate structures with specific metal layers in CMOS devices, where n-type and p-type work function metal layers are used to tailor the work function for corresponding semiconductor devices, with processes that include forming gate stacks, source and drain regions, and dielectric layers to optimize the gate structures for both n-type and p-type devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-k dielectric materials are used to maintain field effect performance during scaling, then equivalent field effect performance is achieved, but the gate structure complexity increases due to the need for different work function metals for n-type and p-type devices
Solution Approach 1:
The patent applies local quality by using different work function metal layers in different regions of the gate structure. Specifically, a first work function metal layer is used for the n-type transistor region while a second work function metal layer is used for the p-type transistor region, allowing each region to have optimized local properties for its specific device type while sharing the same high-k dielectric layer.
2Reliability
If separate gate structure processes are used for n-type and p-type devices, then optimized work functions are achieved, but manufacturing complexity and process steps increase
Solution Approach 1:
The patent segments the gate structure formation process into distinct regions. The method forms a first gate structure with a first work function metal layer for the n-type transistor, and a second gate structure with a second work function metal layer for the p-type transistor, allowing separate optimization of each device type while maintaining a unified high-k dielectric layer that simplifies the overall manufacturing process.
Data Source
AI summary
In one embodiment, the method for forming a complementary metal oxide semiconductor (CMOS) device includes providing a semiconductor substrate including a first device region and a second device region. An n-type conductivity semiconductor device is formed in one of the first device region or the second device region using a gate structure first process, in which the n-type conductivity semiconductor device includes a gate structure having an n-type work function metal layer. A p-type conductivity semiconductor device is formed in the other of the first device region or the second device region using a gate structure last process, in which the p-type conductivity semiconductor device includes a gate structure including a p-type work function metal layer.