CMOS Gate Workfunction Control via Interfacial Layers
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Solution Overview
Problem
Current FET devices face challenges in maintaining performance improvements as they are scaled down, particularly in achieving precise threshold voltage control for both n-type and p-type FETs in CMOS circuits, with existing techniques failing to effectively shift the effective-workfunction of the gate in the p-direction.
Innovation Solution
The introduction of a p-type interfacial control layer (PICL) within the gate insulator, typically 0.1 nm to 1.5 nm thick, made of materials like aluminum oxide or aluminum nitride, in conjunction with a high-k dielectric and a common metal gate material for both n-type and p-type FETs, allows for threshold voltage adjustment in the positive direction without altering other device characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a common metal gate material is used for both n-type and p-type FETs, then fabrication complexity is reduced and processing steps are simplified, but precise threshold voltage control for both device types becomes difficult to achieve
Solution Approach 1:
The gate insulator is segmented into multiple functional layers: a high-k dielectric layer for capacitance enhancement and interfacial control layers (NICL for n-type, PICL for p-type) for threshold voltage control. This segmentation allows each layer to independently optimize for its specific function while using a common metal gate material for both device types.
Solution Approach 2:
Different interfacial control layer materials are applied locally to different device regions: NICL materials (e.g., La2O3, MgO) are used for n-type FETs to shift threshold voltage in the negative direction, while PICL materials (e.g., Al2O3, AlN) are used for p-type FETs to shift threshold voltage in the positive direction. This local differentiation enables precise threshold control despite using identical metal gate material throughout.
2Power
If high-k dielectric materials are used to increase gate capacitance, then gate-to-channel capacitance is enhanced without reducing gate dielectric thickness, but control over the effective-workfunction of the gate in the p-direction is lost
Solution Approach 1:
Interfacial control layers serve as intermediary elements between the high-k dielectric and the metal gate. These thin layers (0.1-1.5 nm) mediate the electrical interface, allowing the high-k dielectric to provide enhanced capacitance while the ICL materials independently control the effective-workfunction. The ICL acts as a buffer that decouples the capacitance function from the workfunction control function.
Solution Approach 2:
The gate insulator structure becomes a composite material system combining high-k dielectric materials (e.g., HfO2, HfSiO) with interfacial control layer materials (e.g., Al2O3, La2O3, MgO). This composite structure integrates the high capacitance property of the high-k material with the threshold voltage control property of the ICL materials, achieving both enhanced power and precise workfunction control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the achievement of desired threshold values for p-type FETs while simplifying the fabrication process by using the same gate metal and high-k dielectric for both device types, reducing processing steps and costs, and allowing for precise control of threshold voltages.
Implementation Method 1
Specific layers of threshold modifying materials, so called interface control layers (ICL), have been introduced into n-type FET gate insulators for the purpose of favorably adjusting the effective-workfunction of the gate
Implementation Method 2
The dielectric constant of such materials is significantly higher than that of SiO2, which is about 3.9. A high-k material may physically be significantly thicker than an oxide, and still have a lower equivalent oxide thickness (EOT) value
Implementation Method 3
Metal gates also assure good conductivity along the width direction of the devices, reducing possible RC delays in the gate
Data Source
AI summary
CMOS circuit structures are disclosed with the PFET and NFET devices having high-k dielectric layers consisting of the same gate insulator material, and metal gate layers consisting of the same gate metal material. The PFET device has a “p” interface control layer which is capable of shifting the effective-workfunction of the gate in the p-direction. In a representative embodiment of the invention the “p” interface control layer is aluminum oxide. The NFET device may have an “n” interface control layer. The materials of the “p” and “n” interface control layers are differing materials. The “p” and “n” interface control layers are positioned to the opposite sides of their corresponding high-k dielectric layers. Methods for fabricating the CMOS circuit structures with the oppositely positioned “p” and “n” interface control layers are also disclosed.