CMOS GOA Circuit Reducing TFT Count for Narrow Border Displays
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Solution Overview
Problem
Current CMOS gate driver on array (GOA) circuits for LCDs require a large number of thin-film transistors (TFTs), making them unsuitable for narrow border displays, as they use NAND gate circuits which are not efficient for reducing border size.
Innovation Solution
A CMOS GOA circuit design that cascades odd-numbered and even-numbered stages, incorporating a forward-and-backward scan control module, control input module, reset module, latch module, and signal processing module with a reduced number of TFTs, allowing for efficient scanning and reduced border size by alternating voltage signals and clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional NAND gate circuit is used in CMOS GOA circuit, then signal processing function is achieved, but the number of TFTs increases making it unsuitable for narrow border displays
Solution Approach 1:
The patent combines multiple functions into a single integrated circuit block. The GOA circuit integrates the scan signal generation, signal processing, and output driving functions into one unified structure, eliminating the need for separate NAND gate circuits and reducing the total TFT count from 4 to 3 per pixel row control
Solution Approach 2:
The circuit performs multiple functions simultaneously: it generates scan signals, processes input signals through clocked logic, provides reset functionality, and outputs driving signals all within a single circuit architecture that supports both forward and backward scanning modes
2Length of moving object
If more TFTs are used in GOA circuit, then circuit functionality is enhanced, but border size increases
Solution Approach 1:
The patent extracts and eliminates redundant components from the traditional GOA circuit design. By removing the unnecessary NAND gate circuitry and integrating its functions directly into the clocked signal processing paths, the design reduces TFT count while maintaining all essential GOA functionalities
Solution Approach 2:
Instead of adding more TFTs to enhance functionality as in traditional designs, the patent inverts the approach by reducing TFT count and achieving enhanced functionality through more efficient circuit architecture and multi-function integration
Data Source
AI summary
The invention provides a CMOS GOA circuit, comprising a signal processing module having a first and a second TFTs, the first TFT having a gate connected to a first control signal, a source connected to an output node and a drain connected to a third node; the second TFT having a gate and a source connected to a second control signal, and a drain connected to the third node; the first and second control signals having opposite phases, the first and second control signals controlling the first and second TFTs to turn on alternatingly inputting a voltage signal of the output node or a second control signal to the third node. Compared to the known technique using NAND circuit, the invention reduces the number of TFTs required by latch module without affecting operation of the circuit, and facilitates the implementation of the ultra-narrow border or borderless display products.