CMOS GOA Circuit Reducing Clock Signal Loading

Solution Overview

Problem

The CMOS GOA circuit faces significant clock signal loading due to the large number of thin film transistors driven by the clock signal, leading to increased RC delay and power consumption.

Innovation Solution

The proposed CMOS GOA circuit reduces clock signal loading by cascading GOA units of odd and even stages, utilizing an input control module, latch module, reset module, and signal process module to minimize the number of transistors controlled by the clock signal, specifically using the inverted scan drive signal and scan drive signal as input and pull-down control signals to prevent competition.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the clock signal controls multiple thin film transistors (T4, T6, T10, T11) in the prior art CMOS GOA circuit, then the circuit can achieve complete reset and latch functions, but the clock signal loading increases significantly leading to increased RC delay and power consumption

Engineering Contradiction:

Improvereset and latch function completenessVSAvoidclock signal power consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent segments the clock signal control function by introducing a dedicated control signal (SCK) for the switch transistor Tsw, separating it from the main clock signal CK. This allows the clock signal to control fewer transistors (reducing loading) while the control signal handles the reset function, maintaining complete reset and latch functionality through distributed control across multiple signals.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary control signal SCK that mediates between the clock signal CK and the switch transistor Tsw. Instead of the clock signal directly controlling multiple transistors, it uses SCK as an intermediary to activate Tsw, thereby reducing the clock signal's loading while preserving the reset function.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If the clock signal controls multiple thin film transistors in the prior art CMOS GOA circuit, then the circuit achieves complete reset and latch functions, but the RC delay of the clock signal increases

Engineering Contradiction:

Improvereset and latch function completenessVSAvoidclock signal RC delay

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent segments the clock signal control function by introducing a dedicated control signal (SCK) for the switch transistor Tsw, separating it from the main clock signal CK. This allows the clock signal to control fewer transistors (reducing loading) while the control signal handles the reset function, maintaining complete reset and latch functionality through distributed control across multiple signals.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary control signal SCK that mediates between the clock signal CK and the switch transistor Tsw. Instead of the clock signal directly controlling multiple transistors, it uses SCK as an intermediary to activate Tsw, thereby reducing the clock signal's loading while preserving the reset function.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Reliability

If the clock signal controls multiple thin film transistors (T4, T6, T10, T11) in the prior art CMOS GOA circuit, then the circuit achieves complete reset and latch functions, but the device complexity increases

Engineering Contradiction:

Improvereset and latch function completenessVSAvoidcircuit structure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the clock signal control function by introducing a dedicated control signal (SCK) for the switch transistor Tsw, separating it from the main clock signal CK. This allows the clock signal to control fewer transistors (reducing loading) while the control signal handles the reset function, maintaining complete reset and latch functionality through distributed control across multiple signals.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary control signal SCK that mediates between the clock signal CK and the switch transistor Tsw. Instead of the clock signal directly controlling multiple transistors, it uses SCK as an intermediary to activate Tsw, thereby reducing the clock signal's loading while preserving the reset function.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS10032425B2CMOS GOA circuit of reducing clock signal loading

Publication Date: 2018.07.24 WUHAN CHINA STAR OPTOELECTRONICS TECH CO LTD

AI summary

The CMOS GOA circuit of reducing clock signal loading comprises the input control module (1), the latch module (2), the reset module (3), the signal process module (4) and the output buffer module (5); in the input control module (1), the clock signal (CK(M)) merely needs to control the second N type thin film transistor and the fifth N type thin film transistor (T2, T5), and the amount of the thin film transistors driven by the clock signal can be decreased to reduce the clock signal loading, and to lower the RC delay and the power consumption of the clock signal; the latch module (2) utilizes the inverted scan drive signal (XGate(N−2)) of the two former N-2th stage GOA unit to be the input control signal of the stage transfer signal Q(N) to solve the competition problem occurs as the stage transfer signal (Q(N)) is inputted.