CMOS GOA Circuit Feedback Regulation for RC Delay
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Solution Overview
Problem
The existing CMOS gate driver array (GOA) circuits experience significant RC delay in signal propagation, leading to abnormal display issues, particularly when driving high-resolution panels, due to the large resistor-capacitor (RC) loading and resulting delays in clock signals.
Innovation Solution
The proposed CMOS GOA circuit incorporates a feedback regulation module with P-type and N-type thin film transistors (TFTs) to enhance the pull-up and pull-down capabilities of the signal processing module, reducing the RC loading by using an odd-number of serially connected inverters and specific TFT configurations to expedite the rising and falling times of the scan driver signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the existing CMOS GOA circuit uses standard signal processing modules, then the circuit structure is simple, but the RC loading is large causing significant signal propagation delay
Solution Approach 1:
The patent introduces a feedback regulation module that samples the output signal and feeds it back to the input side. This feedback mechanism dynamically adjusts the signal processing to compensate for RC delays, thereby reducing signal propagation delay without significantly increasing circuit complexity
Solution Approach 2:
The patent modifies the signal processing parameters by using an odd number of inverters in the feedback path and adjusting the threshold voltages of transistors. These parameter changes optimize the signal waveform and reduce RC loading effects, improving signal propagation speed
2Area of stationary object
If the clock signal propagates through long distances in the existing CMOS GOA circuit, then the circuit can drive large panels, but the clock signal experiences large RC delay causing signal deformation
Solution Approach 1:
The patent divides the long clock signal path into multiple stages, each with its own buffer and feedback regulation. This segmentation reduces the effective propagation distance in each stage, minimizing cumulative RC delays and maintaining clock signal integrity across large panels
Solution Approach 2:
The patent introduces intermediate buffer stages and feedback regulation modules along the clock signal path. These intermediaries actively compensate for signal degradation, maintaining clock signal integrity over long propagation distances required for large panel driving
3Stability of the object's composition
If the scan driver signal has slow rising and falling times in the existing CMOS GOA circuit, then the transistor switching is gentle, but the RC loading increases causing abnormal display
Solution Approach 1:
The patent uses periodic clock signals with optimized duty cycles and frequencies to drive the scan driver. This periodic action ensures that transistors switch at optimal moments, maintaining smooth switching while the feedback regulation prevents excessive RC loading that would cause display abnormalities
Solution Approach 2:
The patent adjusts the switching parameters by modifying transistor threshold voltages and using an odd number of inverters in the feedback path. These parameter changes optimize the rising and falling edges of the scan driver signal, maintaining smooth transitions while reducing RC loading effects that cause display defects
Data Source
AI summary
The invention provides a CMOS GOA circuit, by disposing a feedback regulation module (4) connected to output buffer module (3) and signal processing module (2) in the GOA unit, to achieve the following: when the scan driver signal (G(N)) becomes high, the positive feedback from the sixth N-type TFT (T6) of feedback regulation module (4) will enhance the pull-down capability of the signal processing module (2) to reduce the rising time of the scan driver signal (G(N)) waveform; when the scan driver signal (G(N)) becomes low, the positive feedback from the fifth P-type TFT (T5) of feedback regulation module (4) will enhance the pull-up capability of the signal processing module (2) to reduce the falling time of scan driver signal (G(N)) waveform; that is, the invention can reduce the RC loading of scan driver signal (G(N)) and improve the stability of high resolution display panel.