CMOS Image Sensor Hard Mask Retention for Process Simplification
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Solution Overview
Problem
The manufacturing process for CMOS image sensors is complex, time-consuming, and costly due to the need for additional photolithography and etching operations to remove a portion of the hard mask layer in the logic region, which complicates the process and increases costs.
Innovation Solution
By controlling the parameters of the operation for forming sources and drains, the pixel performance of the semiconductor device is maintained without the need to remove the hard mask layer in the logic region, thereby simplifying the process, reducing time, and lowering costs by eliminating the need for additional photolithography and etching operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If additional photolithography and etching operations are performed to remove the hard mask layer in the logic region, then the manufacturing precision is improved, but the device complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts the hard mask layer removal operation from the manufacturing process by maintaining the hard mask layer in the logic region. This eliminates the need for additional photolithography and etching operations to remove the hard mask layer, while still achieving the desired manufacturing precision through selective spacer formation and source/drain processing in the photosensitive region.
Solution Approach 2:
The patent segments the substrate into logic region and photosensitive region, applying different processing strategies to each. The hard mask layer is maintained in the logic region while being selectively removed or processed in the photosensitive region, allowing precision work in the photosensitive area without requiring additional removal steps for the entire device.
2Manufacturing precision
If additional photolithography and etching operations are performed to remove the hard mask layer in the logic region, then the manufacturing precision is improved, but the production time increases
Solution Approach 1:
The patent extracts the hard mask layer removal operation from the manufacturing process by maintaining the hard mask layer in the logic region. This eliminates the need for additional photolithography and etching operations, directly reducing production time while maintaining necessary precision through alternative processing methods in the photosensitive region.
Solution Approach 2:
The patent performs preliminary selective processing during the spacer formation step, where the spacer material layer is selectively removed to expose the hard mask layer only in the photosensitive region. This preliminary action eliminates the need for subsequent removal operations, saving time in the overall manufacturing process.
3Manufacturing precision
If additional photolithography and etching operations are performed to remove the hard mask layer in the logic region, then the manufacturing precision is improved, but the manufacturing cost increases
Solution Approach 1:
The patent extracts the hard mask layer removal operation from the manufacturing process by maintaining the hard mask layer in the logic region. This eliminates the need for additional photolithography and etching operations, directly reducing manufacturing costs while maintaining necessary precision through alternative processing methods in the photosensitive region.
Solution Approach 2:
The hard mask layer serves multiple functions: it protects the logic region from damage during source/drain implantation and serves as a mask for spacer formation in the photosensitive region. By maintaining the hard mask layer in the logic region, the patent eliminates the need for separate removal operations, reducing manufacturing complexity and cost.
Data Source
AI summary
A semiconductor device includes a substrate, a logic gate structure, a photosensitive gate structure, a hard mask layer, a first spacer, a first source, a first drain, a second spacer, a second source and a second drain. The logic gate structure and the photosensitive gate structure are disposed on a surface of the substrate. The hard mask layer covers the logic gate structure, the photosensitive gate structure and the surface of the substrate. The first spacer overlies the hard mask layer conformal to a sidewall of the logic gate structure. The first source and drain are respectively disposed in the substrate at two opposite sides of the logic gate structure. The second spacer overlies the hard mask layer conformal to a sidewall of the photosensitive gate structure. The second source and drain are respectively disposed in the substrate at two opposite sides of the photosensitive gate structure.