CMOS-HBT Integration on Single Die for RFFE Parasitic Reduction
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Solution Overview
Problem
The integration of complementary metal oxide semiconductor (CMOS) devices and heterojunction bipolar transistors (HBTs) on a single die is hindered by the use of different materials and wafer sizes, leading to high parasitic resistance, large size, and increased cost and cycle time in radio frequency front end (RFFE) modules, particularly at high frequency bands like 5G.
Innovation Solution
A method is developed to fabricate HBTs using III-V materials on a Silicon substrate, integrating them with CMOS devices on a single die, involving the formation of layers, patterning, and bonding with SiO2 layers to reduce parasitics and enable cost and cycle time savings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If CMOS devices and PAs are assembled as discrete components on a laminate substrate, then fabrication can be done in separate facilities, but this leads to high parasitic resistance, high parasitic inductance, high parasitic capacitance, large size, and increased cost and cycle time
Solution Approach 1:
The patent merges CMOS devices and HBT-based PAs onto a single integrated circuit die, eliminating the need for separate fabrication facilities and discrete component assembly. This integration directly reduces parasitic resistance, inductance, and capacitance while maintaining the benefit of specialized fabrication processes for each device type.
Solution Approach 2:
The patent uses an intermediary bonding process that bonds the CMOS die and HBT die together using a bonding layer with thickness between 1 nanometer to 10 micrometers. This intermediary bonding layer enables integration of devices from separate fabrication facilities while achieving low parasitic values through direct physical connection.
2Device complexity
If wafer bonding techniques are used to integrate CMOS devices and PAs, then integration on a single die is achieved, but this is impractical due to different wafer sizes (300 mm Si wafers for CMOS vs. 150 mm or 75 mm wafers for III-V materials)
Solution Approach 1:
The patent segments the integration process into two separate stages: first fabricating CMOS devices on 300 mm Si wafers, then separately fabricating HBTs on 150 mm or 75 mm III-V material wafers. The segmented dies are subsequently bonded together, avoiding the need for wafer-level bonding of differently-sized wafers while achieving die-level integration.
Solution Approach 2:
The patent transitions from attempting wafer-level integration (2D plane matching) to die-level integration (3D stacking/bonding). By bonding finished CMOS dies to HBT dies in a vertical dimension, the patent circumvents the wafer size incompatibility issue entirely.
3Adaptability or versatility
If discrete components are used in RFFE modules, then fabrication flexibility is maintained, but this results in large module size and high parasitic values that significantly impact performance at high frequency bands like 5G
Solution Approach 1:
The patent combines CMOS control circuits and HBT power amplifiers into a single integrated circuit die, eliminating the physical separation between components. This merging reduces the loop area and trace length between devices, directly minimizing parasitic inductance and capacitance while preserving fabrication flexibility through modular die design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This integration reduces the size and parasitics of RFFE modules, enhances performance at high frequency bands, and provides cost and cycle time savings by integrating CMOS devices and HBTs on a single die, optimizing power amplifier performance through dynamic impedance tuning.
Implementation Method 1
bonding the first SiO2 layer to a second SiO2 layer covering a CMOS device on a second substrate
Data Source
AI summary
A semiconductor device comprises a complementary metal oxide semiconductor (CMOS) device and a heterojunction bipolar transistor (HBT) integrated on a single die. The CMOS device may comprise silicon. The HBT may comprise III-V materials. The semiconductor device may be employed in a radio frequency front end (RFFE) module to reduce size and parasitics of the RFFE module and to provide cost and cycle time savings.