CMOS High-k Dielectric Layer Formation for EOT Optimization
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Solution Overview
Problem
In semiconductor device manufacturing, particularly for CMOS devices with small feature sizes, the high-k last, metal-gate last method complicates the formation of gate stacks and makes it difficult to optimize the equivalent oxide thickness (EOT) for both NMOS and PMOS regions simultaneously, leading to suboptimal performance and unwanted high-k material residuals at metal gate contact interfaces.
Innovation Solution
A method involving the sequential formation of high-k dielectric and cap layers in separate process steps for NMOS and PMOS regions, with controlled thickness and material differences, followed by selective removal of these layers to minimize residual high-k material at contact interfaces, allowing for individual optimization of EOT for each region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a high-k last, metal-gate last method is used to manufacture CMOS devices with small feature sizes, then the equivalent oxide thickness (EOT) can be made small, but the formation of gate stacks becomes substantially complicated
Solution Approach 1:
The gate stack formation process is segmented into separate steps for NMOS and PMOS regions. First, a first gate stack is formed in the first trench for the PMOS region, then a second gate stack is formed in the second trench for the NMOS region. This segmentation allows each region to be optimized independently while simplifying the overall process compared to forming both simultaneously in a single complex step.
Solution Approach 2:
Different gate stack structures are created for different regions of the semiconductor device. The first gate stack for PMOS and the second gate stack for NMOS can have different compositions, thicknesses, and materials tailored to the specific requirements of each transistor type, enabling local optimization of EOT and performance characteristics.
2Productivity
If NMOS and PMOS are manufactured at the same time with a dual work function metal gate, then both transistor types can be produced in one process, but it becomes substantially difficult to satisfy work function requirements for both regions
Solution Approach 1:
The manufacturing process is divided into separate sequential steps for NMOS and PMOS regions. The first gate stack is formed for PMOS with appropriate work function materials, then the second gate stack is formed for NMOS with different work function materials. This segmentation maintains high productivity by processing both regions in one overall flow while achieving precise work function control for each region independently.
Solution Approach 2:
The work function layers are prepared in advance during the gate stack formation process. By forming the first gate stack with PMOS-appropriate materials before forming the second gate stack with NMOS-appropriate materials, the preliminary preparation of each region's specific material composition enables subsequent precise work function tuning without compromising the other region.
3Manufacturing precision
If gate stacks are manufactured separately for NMOS and PMOS regions, then EOT thickness can be optimized for each region, but unwanted residual high-k material remains at metal gate contact interfaces
Solution Approach 1:
The harmful residual high-k material is selectively removed through a removal step that targets the metal gate contact interfaces. After forming both gate stacks, the process extracts the unwanted high-k material deposits that remain at the contact interfaces, eliminating the source of high gate resistance while preserving the optimized gate stack structures in the active regions.
Solution Approach 2:
The residual high-k material that initially appears harmful is addressed by converting the situation into a benefit: the sequential formation process that creates these residuals also allows for targeted removal steps. The removal process selectively eliminates the harmful residuals at contact interfaces while preserving the beneficial high-k material in the gate dielectric layers, thus converting the harmful presence into a controlled, beneficial configuration.
4Reliability
If residual high-k material remains at metal gate contact interfaces, then the gate stack structure is complete, but gate resistance becomes undesirably high
Solution Approach 1:
The removal step selectively extracts residual high-k material from the metal gate contact interfaces through targeted etching or cleaning processes. This extraction eliminates the high resistance paths caused by high-k material deposits while preserving the intact gate stack structures in the active transistor regions, thereby improving gate conductivity without requiring complete reconstruction of the gate stacks.
Data Source
AI summary
A method for manufacturing a semiconductor device may include the following steps: preparing a substrate having a PMOS region and an NMOS; forming a first gate trench on the PMOS region; forming a first high-k dielectric layer and a first high-k cap layer that cover a bottom and sides of the first gate trench; forming a second gate trench on the NMOS region; forming a second high-k dielectric layer and a second high-k cap layer that cover a bottom and sides of the second gate trench; removing a portion of the first high-k dielectric layer and a portion of the first high-k cap layer that are positioned on a side of the first gate trench; and removing a portion of the second high-k dielectric layer and a portion of the second high-k cap layer that are positioned on a side of the second gate trench.