CMOS-III-V Opposite-Side Assembly With Low-Temperature SiO2 Embedding
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Solution Overview
Problem
Current heterogeneous integration schemes in semiconductor packaging face challenges such as high frequency losses due to horizontal interconnects and thermal management issues in 2D and 3D configurations, particularly in RF and 5G applications, with 2D beam steering being difficult to achieve.
Innovation Solution
A method involving the assembly of CMOS and III-V chips on opposite sides of a substrate, using a stress-compensated SiO2 layer applied at low temperatures to embed one component laterally, with electrical interconnects through semiconductor vias, enabling 3D packaging and avoiding direct bonding-related thermal management problems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If 3D heterogeneous integration is applied to enable 2D beam steering, then space efficiency and beam steering capability are improved, but thermal management becomes problematic
Solution Approach 1:
The patent introduces an interposer substrate as an intermediary component between the CMOS chip and III-V chip. This interposer acts as a thermal management mediator, allowing the chips to be positioned on opposite sides for space efficiency while maintaining separate thermal pathways through the substrate, thus resolving the thermal management issue in 3D integration.
Solution Approach 2:
The patent transitions from horizontal (2D) or direct vertical (3D) integration to a separated vertical arrangement where chips are positioned on opposite sides of the substrate along the Z-axis. This dimensional reorganization allows space-efficient integration while enabling independent thermal management for each chip through the substrate.
2Temperature
If 2.5D heterogeneous integration is applied to improve thermal management, then thermal dissipation is improved, but high frequency losses occur due to horizontal interconnects
Solution Approach 1:
The patent eliminates horizontal interconnects by positioning the CMOS chip and III-V chip on opposite sides of the substrate and connecting them through vertical via structures. This dimensional change from horizontal to vertical interconnection removes the source of high frequency losses while maintaining thermal management benefits.
Solution Approach 2:
The patent extracts and removes the horizontal interconnect structures that cause high frequency losses. By replacing them with vertical via connections through the substrate, the harmful horizontal signal paths are eliminated while preserving the thermal management advantages of separated chip positioning.
3Reliability
If stress-compensated SiO2 layer is applied at low temperatures to embed component, then component functionality is maintained and substrate warping is prevented, but manufacturing complexity increases
Solution Approach 1:
The patent changes the deposition temperature parameter to low temperatures during SiO2 layer formation, preventing thermal damage to the embedded component. Additionally, stress compensation parameters are adjusted by creating a multi-layer structure with alternating materials of different thermal expansion coefficients, balancing the overall stress to prevent substrate warping.
Solution Approach 2:
The patent employs a composite multi-layer SiO2 structure with alternating layers of different materials and stress characteristics. This composite approach compensates for thermal stress while maintaining component functionality, though it does increase manufacturing complexity through multiple deposition steps.
4Area of stationary object
If components are directly bonded to achieve compact integration, then integration density is improved, but thermal management problems arise
Solution Approach 1:
The patent positions the CMOS chip and III-V chip on opposite sides of the substrate along the vertical Z-axis, achieving compact integration in the vertical dimension while maintaining thermal separation. This eliminates direct thermal contact between the chips, allowing each to be managed independently through the substrate.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables short, low-loss interconnects and 2D beam steering by allowing space-efficient integration of CMOS and III-V components, while maintaining component functionality and preventing substrate warping during processing.
Implementation Method 1
The example embodiments are related to a heterogeneous integration scheme, i.e. the assembly of components of different types, in particular a CMOS (complementary metal-oxide semiconductor) chip and a III-V chip
Implementation Method 2
The fact that the stress-compensated film is applied at temperatures which do not compromise the functionality of the component embedded in the film, together with the fact that the film is stress-compensated enables mounting the component on one side of the substrate and continuing to process the substrate on the opposite side thereof, without unallowable warping of the substrate
Data Source
AI summary
The method of the present disclosure is related to the assembly of two components on two opposite sides of a substrate, enabled by the embedding of one of the components in a stress-compensated SiO2 layer applied at low temperatures, i.e. lower than any temperature that could compromise the functionality of the embedded component. Example embodiments are related to heterogeneous integration schemes, i.e. the assembly of components of different types, in particular a CMOS chip and a III-V chip, which are otherwise difficult to integrate in a 3D package. The stress-compensated film embeds the component at least laterally, i.e. the layer surrounds and is in direct contact with the sides of the component and the thickness of the film is at least equal to the thickness of the component.