CMOS Image Sensor Binning Circuit for Resolution and Power
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Solution Overview
Problem
Current image sensing devices face challenges in efficiently performing column and row binning operations, which are essential for enhancing image resolution and data processing in digital cameras, particularly due to complex driving schemes and high power consumption in CCDs, and limitations in monolithic integration in CMOS image sensors.
Innovation Solution
An image sensing device and method that enables simultaneous column and row binning operations by using a sampling unit to average and store signals from unit pixels, with a gain adjusting unit for amplification, allowing for efficient data processing and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If column and row binning operations are performed sequentially using traditional methods, then the operations can be completed, but the processing time increases and productivity decreases
Solution Approach 1:
The patent merges column binning and row binning operations into a single integrated circuit structure where both operations are performed simultaneously. The column binning unit and row binning unit are combined in a pipelined architecture, allowing data to flow through both binning stages without sequential delays, thus improving productivity and reducing processing time.
Solution Approach 2:
The column binning operation is performed as a preliminary step before row binning in a pipelined manner. By pre-processing the data through column binning and preparing intermediate results in storage units, the system enables faster subsequent row binning operations, effectively reducing the total processing time while maintaining high productivity.
2Measurement precision
If binning mode is implemented to increase resolution, then image quality improves, but additional circuit area is required
Solution Approach 1:
The patent implements a universal binning circuit structure that can perform both column binning and row binning operations using the same hardware resources. The sampling unit, storage units, and gain adjusting units are designed to be multi-functional, handling different binning operations without requiring separate dedicated circuits for each function, thereby minimizing the additional circuit area while maintaining high image resolution.
Solution Approach 2:
The circuit is designed with dynamic switching capabilities that allow the same hardware resources to be allocated flexibly between column and row binning operations based on real-time requirements. This dynamic resource allocation enables the system to achieve high resolution binning mode when needed while minimizing the permanent circuit area overhead by sharing resources across different operational modes.
3Reliability
If signal amplification is performed for binning operations, then signal quality improves, but power consumption increases
Solution Approach 1:
The patent applies gain adjusting units selectively and locally only to the specific signal paths that require amplification during binning operations, rather than amplifying all signals throughout the circuit. This localized amplification approach maintains high signal quality where needed while minimizing unnecessary power consumption in other parts of the circuit, effectively resolving the contradiction between signal quality and power consumption.
Data Source
AI summary
An image sensing device includes a plurality of pixels arranged in rows and columns and a sampling unit suitable for sampling the plurality of pixels in units of M by N in a binning mode, M and N being a positive integer greater than 2.