CMOS Image Sensor Block Memory Architecture for Readout Speed
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Solution Overview
Problem
High-speed CMOS image sensor circuits face bottlenecks in memory readout operations due to long readout bus lengths, leading to signal degradation, increased power consumption, and digital noise, as well as delays in sending control signals to column ADC circuits, which limit processing speed and image quality.
Innovation Solution
The implementation of a block memory architecture with memory blocks located on either side of the pixel array, reducing the length of readout buses and the number of memory cells connected to each bit line, thereby decreasing resistance and capacitance, and using multiple ADC controllers to reduce control signal propagation delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a single memory block is used to store digital pixel signals from all column ADC circuits, then the memory capacity is sufficient, but the readout bus length becomes excessively long causing signal degradation and increased power consumption
Solution Approach 1:
The patent divides the single memory block into multiple smaller memory blocks (e.g., first memory block and second memory block). Each memory block is connected to a subset of column ADC circuits, thereby reducing the readout bus length for each block and minimizing signal degradation while collectively maintaining sufficient storage capacity for all pixel signals
2Quantity of substance
If a single memory block with long readout bus is used, then all digital pixel signals can be stored, but power consumption increases due to long signal transmission distances
Solution Approach 1:
The patent segments the memory system into multiple blocks, each serving a specific region of column ADC circuits. This reduces the average transmission distance for digital signals within each memory block, thereby lowering the overall power consumption while maintaining the total memory capacity needed for all pixel data
3Length of moving object
If memory blocks are distributed on both sides of the pixel array, then readout bus length is reduced, but the device complexity increases
Solution Approach 1:
The patent divides the memory system into multiple blocks positioned on both sides of the pixel array, with each block serving a specific region. This segmentation reduces readout bus length for each block while the modular design allows for systematic management of the distributed configuration, balancing the trade-off between reduced bus length and increased device complexity
4Device complexity
If control signals are sent from a single ADC controller to all column ADC circuits, then the control logic is simplified, but signal propagation delays increase
Solution Approach 1:
The patent divides the control system into multiple ADC controllers, with each controller managing a specific group of column ADC circuits. This segmentation reduces the propagation delay for control signals within each group while the modular controller architecture allows for simplified individual controller designs, effectively balancing control logic simplicity with signal transmission speed
Data Source
AI summary
An image sensor circuit includes a pixel array, a plurality of column analog-to-digital conversion (ADC) circuits, and at least two memory blocks. Each column ADC circuit is connected to receive analog pixel signals provided from corresponding pixel circuits of the pixel array, and is configured to convert the received analog pixel signals into digital pixel signals. Each memory block is connected to receive digital pixel signals provided from corresponding column ADC circuits of the plurality of column ADC circuits. At least two of the at least two memory blocks are connected to receive digital pixel signals that are provided from corresponding column ADC circuits that are located to a same side of the pixel array. Each memory block of the at least two memory blocks includes a plurality of memory cells, one or more sense amplifiers connected to the memory cells by a readout bus, and a memory controller.