CMOS Image Sensor Bonding Process Using Through-Wafer Vias
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Solution Overview
Problem
Current semiconductor integrated circuit devices face issues such as increased chip size due to doubled bond pads, reliability problems with metal interconnects, and packaging issues caused by step heights and dielectric film cracking.
Innovation Solution
A method involving forming a top metal pad on the substrate, embedding it in a passivation layer, creating a deep trench, filling it with conductive material to form a through-wafer via feature, and using chemical mechanical polishing to create a planar surface, thereby reducing chip size and improving reliability by eliminating step heights and dielectric film cracking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If extension pads are added to the bond pad structure, then the number of pads is doubled to meet connection requirements, but the chip size is enlarged
Solution Approach 1:
The patent transitions from a planar pad arrangement to a three-dimensional structure by forming pads that extend through the substrate thickness. The pad structure moves from being confined to the surface plane to occupying vertical space, allowing connection functionality to be achieved without increasing the horizontal chip footprint.
Solution Approach 2:
The pad structure is nested within the substrate by forming conductive regions that extend from the front surface through the substrate to the back surface. The pad is embedded within the substrate volume rather than being added as an external extension, integrating the connection function into the substrate itself.
2Reliability
If metal interconnects are used to connect bond pads to the front side, then electrical connection is achieved, but reliability problems occur
Solution Approach 1:
The patent extracts the metal interconnect layer from the structure by removing it after the pad formation process. This eliminates the metal interconnect component that causes reliability issues while preserving the electrical connection function through the through-substrate pad structure.
Solution Approach 2:
The dielectric material serves as an intermediary between the conductive pad regions at the front and back surfaces. Instead of using metal interconnects to bridge the connection, the dielectric-embedded conductive structure provides the electrical pathway, mediating the connection without the reliability problems of metal interlayers.
3Area of stationary object
If a through silicon via structure is formed to connect front and back sides, then chip size is reduced, but step height causes packaging issues
Solution Approach 1:
The patent merges the pad formation and via formation processes into a single integrated structure. The conductive pad region continuously extends from the front surface through the substrate to the back surface, eliminating the separate via structure and its associated step height. The pad and via become one unified conductive element.
Solution Approach 2:
The pad structure is formed to extend through the entire substrate thickness before any subsequent processing steps. By establishing the through-substrate conductive path in advance, the structure is prepared to accommodate subsequent planarization or packaging processes without creating problematic surface steps.
4Reliability
If dielectric film is applied over the structure, then protection is provided, but cracking and moisture issues occur
Solution Approach 1:
The patent applies different dielectric materials or dielectric structures at different locations within the device. The dielectric properties are optimized locally - for example, using different dielectric constants or mechanical properties in different regions to prevent cracking while maintaining protection functionality and reducing moisture susceptibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces chip size, enhances reliability by eliminating step heights and dielectric film cracking, and improves packaging efficiency by forming a planar surface and connecting the top metal pad to the through-wafer via feature.
Implementation Method 1
applying a polishing process to remove excessive conductive material, forming a substantially planar surface
Data Source
AI summary
The present disclosure provides a method of making an integrated circuit (IC). The method includes forming an electric device on a front side of a substrate; forming a top metal pad on the front side of the substrate, the top metal pad being coupled to the electric device; forming a passivation layer on the front side of the substrate, the top metal pad being embedded in the passivation layer; forming an opening in the passivation layer, exposing the top metal pad; forming a deep trench in the substrate; filling a conductive material in the deep trench and the opening, resulting in a though-wafer via (TWV) feature in the deep trench and a pad-TWV feature in the opening, where the top metal pad being connected to the TWV feature through the pad-TWV feature; and applying a polishing process to remove excessive conductive material, forming a substantially planar surface.