CMOS Image Sensor Buried Contact Structure

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Solution Overview

Problem

The existing CMOS image sensors face limitations in reducing the overall size and improving photosensitivity due to the large area occupied by the contact regions in the CMOS logic circuit part, which restricts the integration and efficiency of the device.

Innovation Solution

The CMOS image sensor design minimizes the contact region area by using a buried contact structure with a first and second contact that are sequentially stacked to directly connect the third gate to the floating diffusion region, eliminating the need for metallic wiring lines and allowing for a more compact CMOS logic circuit part, thereby increasing the photodiode area ratio.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If a conventional contact structure with separate first and second contacts connected by metallic wiring lines is used, then the electrical connection between the third gate and floating diffusion region is established, but the contact region occupies large area which limits integration and photosensitivity

Engineering Contradiction:
Improvecontact region areaVSAvoidelectrical connection reliability
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The first contact and second contact are merged into a single vertically stacked contact structure. The first contact extends from the third gate through the insulating layer, and the second contact extends from the first contact to the floating diffusion region, creating a unified conductive path that eliminates the need for separate lateral wiring lines and reduces the overall contact region area.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The contact structure transitions from a lateral two-dimensional layout with separate contacts connected by wiring lines to a vertical three-dimensional stacked structure. This dimensional change allows the electrical connection to be established through the vertical dimension rather than requiring extensive lateral space, thereby reducing the contact region area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If the photodiode area is increased to improve photosensitivity, then the light detection capability is enhanced, but the overall device area increases which limits integration

Engineering Contradiction:
ImprovephotosensitivityVSAvoiddevice area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The stacked contact structure utilizes the vertical dimension to establish electrical connections, freeing up lateral space. This allows the photodiode area to be maximized within the available device footprint without requiring additional lateral space for contact wiring, thereby improving photosensitivity without proportionally increasing the overall device area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS7573082B2CMOS image sensor and method of fabricating the same
Publication Date: 2009.08.11 MAGNACHIP SEMICON LTD
  • US7573082B2 patent drawing
  • US7573082B2 patent drawing
  • US7573082B2 patent drawing

AI summary

A CMOS image sensor and a method of fabricating the same are provided. In the CMOS image sensor, a device isolation layer is formed in a substrate to define an active region, and a photodiode is formed in the active region. A floating diffusion region is formed at a position spaced apart from the photodiode, and first and second gates are overlapped with one end of the photodiode and one end of the floating diffusion region, respectively. A third gate is disposed between the first gate and the second gate and overlapped with an upper portion of the device isolation layer and a predetermined portion of the floating diffusion region. An insulating layer is formed on the resulting structure where the third gate is formed. A buried contact has a first contact and a second contact, which are sequentially stacked to pass through the insulating layer and the third gate and to connect the third gate to the floating diffusion region disposed under the third gate.