CMOS Image Sensor Capacitance Addition Transistor Gate Voltage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The operation of capacitance addition transistors in imaging devices, such as CMOS image sensors, leads to image quality deterioration due to the rapid voltage changes during signal output, causing charge injection and potential drops that result in signal saturation.
Innovation Solution
The imaging device incorporates a capacitance addition transistor that is turned on and off by changing the gate voltage, with a controlled voltage change rate to minimize charge injection and potential drops, using a drive circuit to manage the gate voltage transitions, ensuring a smaller voltage change amount per unit time when turning off the transistor compared to turning it on.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the capacitance addition transistor is operated rapidly to switch capacitance values, then the dynamic range expansion is achieved, but charge injection and signal saturation occur causing image quality deterioration
Solution Approach 1:
The patent applies periodic action by using correlated double sampling (CDS) to periodically sample and subtract reset level signals from signal level signals. This periodic sampling process eliminates charge injection artifacts and reset level variations that occur during capacitance switching, thereby maintaining image quality while enabling dynamic range expansion through capacitance addition transistor operation
Solution Approach 2:
The patent converts the harmful charge injection effect into a beneficial signal by intentionally sampling it during the reset phase and then subtracting it from the actual signal phase. The charge injection that would normally corrupt the image data is instead captured as a separate measurable quantity and removed through digital signal processing, transforming this harmful side effect into a controllable parameter
2Speed
If the gate voltage changes rapidly to turn on/off the capacitance addition transistor, then the response speed is improved, but voltage drops and charge injection occur leading to signal saturation
Solution Approach 1:
The patent applies preliminary action by performing a reset operation before the actual signal readout. During this preliminary reset phase, the capacitance addition transistor is activated and its charge injection effects are captured in a reset level signal. This preliminary sampling allows the system to prepare compensation data before the main signal acquisition, ensuring that subsequent signal readings are not corrupted by these effects
Solution Approach 2:
The patent implements feedback through the correlated double sampling process where the reset level signal (containing charge injection artifacts) is subtracted from the signal level signal. This feedback mechanism continuously monitors and eliminates the harmful effects of rapid voltage changes, allowing the system to maintain signal accuracy even when operating the capacitance addition transistor at high speeds
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces image quality deterioration by minimizing charge injection and signal saturation, maintaining image quality while expanding the dynamic range by effectively managing the capacitance value of the floating diffusion portion.
Implementation Method 1
a photoelectric converter
Data Source
AI summary
In an imaging device according to the present disclosure, during a period in which a signal from an amplifier transistor is output from a pixel via a select transistor, the gate voltage of the capacitance addition transistor changes frons the first voltage VH to the second voltage VL, and the amount of voltage change per time until the gate voltage changes from the first voltage VH to the second voltage VL is smaller than the amount of voltage change per unit time until the gate voltage changes from the second voltage VL to the first voltage VH.


