Stacked CMOS Image Sensor Capacitor Trench Design
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Solution Overview
Problem
Existing CMOS image sensors have a relatively small fill factor and generate noise such as kTC thermal noise due to limitations in their fabrication methods.
Innovation Solution
A method for fabricating CMOS image sensors involving the formation of capacitors with increased capacitance values by creating etched trenches with sub-trenches, which enhances the capacitance and reduces thermal noise, and a stacked structure with separate signal processing, capacitor, and image sensor layers for improved integration and fill factor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional CMOS image sensor fabrication methods are used, then manufacturing simplicity is maintained, but fill factor remains small and thermal noise is generated
Solution Approach 1:
The patent divides the capacitor formation process into multiple stages by creating sub-trenches within main trenches. This segmentation allows for increased capacitance through larger electrode surface area while maintaining a systematic fabrication approach that balances complexity and performance improvement
Solution Approach 2:
The patent transitions from planar capacitor structures to three-dimensional trench-based capacitors with sub-trenches. This dimensional change increases the electrode surface area and capacitance value without significantly increasing the lateral footprint, thereby improving fill factor while managing fabrication complexity through vertical integration
2Reliability
If capacitor size is increased to reduce thermal noise, then capacitance value increases, but device area increases reducing fill factor
Solution Approach 1:
The patent implements nesting by creating sub-trenches within main trenches, where smaller trenches are positioned inside larger ones. This nested structure maximizes the electrode surface area and capacitance within a compact footprint, reducing thermal noise without significantly increasing the lateral area occupied by the capacitor
Solution Approach 2:
The patent utilizes the vertical dimension by creating deep trenches with multiple sub-levels. This approach increases capacitance through greater electrode surface area in the vertical direction rather than expanding horizontally, thereby reducing thermal noise while maintaining a small footprint that preserves fill factor
3Productivity
If stacked structure with multiple layers is implemented, then integration and fill factor improve, but fabrication process complexity increases
Solution Approach 1:
The patent segments the image sensor into distinct functional layers (photodetector layer, capacitor layer, readout circuit layer) that can be fabricated and optimized independently. This layering approach improves integration efficiency by allowing parallel development of different functions while managing overall device complexity through modular architecture
Solution Approach 2:
The patent transitions from two-dimensional planar integration to three-dimensional stacked architecture. This vertical integration approach increases fill factor by utilizing the third dimension for signal processing and capacitor functions, thereby improving productivity through better space utilization while managing fabrication complexity through standardized bonding and alignment processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method increases the fill factor of CMOS image sensors, reduces thermal noise, and improves the integration and performance of the image sensors by enhancing capacitance values and using a double-bonding technology for mechanical stability.
Implementation Method 1
creating etched trenches with sub-trenches, which enhances the capacitance and reduces thermal noise
Data Source
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AI summary
A method to form a stacked CMOS image sensor includes forming a signal processing layer (200, 201) including a plurality of discrete signal processing circuits, an image sensor layer (300, 301) including a plurality of discrete image sensing units (303), and an intermediate capacitor layer (101, 103, 108) including a dielectric layer (103) and a plurality of capacitors. Each capacitor includes a first electrode (102), a V-shaped or U-shaped first electrode material layer (105) electrically connecting to the first electrode, a second electrode material layer (107) on the first electrode material layer having the dielectric layer there-between, and a second electrode (110) electrically connecting to the second electrode material layer. The method further includes bonding the signal processing layer to the intermediate capacitor layer with each second electrode electrically connected to a signal processing circuit, and bonding the image sensor layer to the intermediate capacitor layer with each first electrode electrically connected to an image sensing unit.