CMOS Image Sensor Dark Current Suppression via Gate Voltage
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Solution Overview
Problem
Solid-state image pickup devices face challenges in achieving a wide dynamic range while maintaining high sensitivity and a high Signal-to-Noise (S/N) ratio, particularly due to excessive dark current components that hinder long-term photoelectric charge accumulation.
Innovation Solution
A CMOS image sensor design with a specific pixel configuration that includes a photodiode, transfer transistor, floating diffusion, accumulating capacitive element, accumulating transistor, and reset transistor, where the gate electrodes of the transfer, accumulating, and reset transistors are set to an OFF voltage level of −0.6 V or lower during the accumulating period, suppressing dark current by forming an np-type or pnp-type embedded channel structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If photoelectric charge is accumulated for a wide dynamic range, then the dynamic range is expanded, but dark current component increases by 3-4 orders of magnitude
Solution Approach 1:
The patent applies a specific voltage parameter (−0.6 V or lower) to the gate electrode of the transfer transistor during the accumulating period. This parameter change creates a potential barrier that suppresses dark current generation at the interface below the gate, while allowing photoelectrons to be accumulated in the floating diffusion and capacitive element, thus resolving the contradiction between wide dynamic range and dark current suppression
Solution Approach 2:
The patent applies a negative voltage to the gate electrode before and during the accumulation period to preemptively suppress dark current generation. This preliminary anti-action prevents the harmful dark current from accumulating in the first place, rather than attempting to remove it afterward, enabling long-term photoelectric charge accumulation without being overwhelmed by dark current
2Object-generated harmful factors
If dark current is suppressed by applying negative voltage to gate electrode, then dark current component is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent utilizes standard CMOS process parameters by applying a conventional negative voltage (−0.6 V or lower) to the gate electrode, which is within the normal operating voltage range of CMOS circuits. This approach suppresses dark current without requiring exotic materials or specialized manufacturing steps, maintaining compatibility with existing CMOS fabrication processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces the dark current component, enabling the accumulation of photoelectric charge over a wide dynamic range with improved sensitivity and S/N ratio.
Implementation Method 1
a photodiode that receives light and generates and accumulates photoelectric charge
Implementation Method 2
an accumulating capacitive element that is connected via said floating diffusion to said photodiode and that at least accumulates the photoelectric charge overflowing from said photodiode
Data Source
AI summary
This invention provides a type of solid-state image pickup device characterized by the fact that for a solid-state image pickup device with a broad dynamic range, it is possible to suppress the dark current than photoelectrons overflowing from the photodiode, as well as its driving method. Plural pixels are integrated in an array configuration on a semiconductor substrate. Each pixel has the following parts: photodiode (CPD), transfer transistor (φT), floating diffusion (CFD), accumulating capacitive element (CS), accumulating transistor (φS), and a reset transistor. During the accumulating period of photoelectric charge, voltage (α) over that applied on the semiconductor substrate, or −0.6 V or lower than the voltage applied on the semiconductor substrate, is applied as an OFF potential on the gate electrode of at least one transfer transistor, the accumulating transistor and the reset transistor.