CMOS Image Sensor Divided Bit Lines for Frame Rate
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Solution Overview
Problem
The frame rate of image sensors is limited by the bit line settling time, which can be improved by reducing bit line capacitance through the division of bit lines into separate portions that are electrically isolated from one another.
Innovation Solution
Dividing column bit lines into 'top' and 'bottom' portions near the middle, each coupled to a single readout circuit through hybrid bonds, reduces the length of the bit line segments and thereby decreases capacitance, allowing for faster settling times and improved frame rates in CMOS image sensors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If bit lines are kept as single long segments, then device complexity is reduced, but bit line settling time increases which limits frame rate
Solution Approach 1:
The bit lines are divided into multiple separate segments (first bit line segment and second bit line segment) that are electrically isolated from each other. Each segment connects to a different readout circuit, which reduces the capacitance of individual bit line segments and thereby decreases the settling time, enabling higher frame rates.
2Loss of time
If bit lines are divided into separate portions, then bit line capacitance is reduced and settling time decreases, but device complexity increases due to additional readout circuits and hybrid bonds
Solution Approach 1:
The bit lines are divided into multiple separate segments (first bit line segment and second bit line segment) that are electrically isolated from each other. Each segment connects to a different readout circuit, which reduces the capacitance of individual bit line segments and thereby decreases the settling time, enabling higher frame rates.
Data Source
AI summary
An image sensor includes a pixel array including a plurality of pixels. A bit line coupled to a column of pixels is separated in to a plurality of electrically portions that are coupled to corresponding portions of rows of the pixel array. A first switching circuit of a readout circuit is coupled to the bit line. A first switching circuit is configured to couple a bit line current source to the bit line to provide a DC current coupled to flow through the bit line and through the first switching circuit during a readout operation of a pixel coupled to the bit line. A second switching circuit is configured to couple and ADC to the bit line during the readout operation of the pixel. Substantially none of the DC current provided by the bit line current source flows through the second switching circuit during the readout operation of the pixel.