CMOS Image Sensor Gate Drive Wiring Layout for Parasitic Capacitance
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Solution Overview
Problem
In CMOS image sensors, the positioning of gate drive lines within a single wiring layer leads to parasitic capacitance, causing propagation delays and differences in accumulation timing across the image sensing region, which degrades image quality, especially in global electronic shutters where precise timing is critical.
Innovation Solution
The gate drive lines for pixel transistors are positioned in a manner that reduces parasitic capacitance by maintaining a maximum wiring distance between them, with specific configurations in each embodiment optimizing the layout to minimize capacitance and delay, such as positioning the gate drive line pTX1 far from pTX2 and using a periodic layout pattern.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If gate drive lines are positioned in a single wiring layer, then device complexity is reduced, but parasitic capacitance increases causing propagation delays
Solution Approach 1:
The patent transitions from a single-plane wiring layout to a three-dimensional multi-layer wiring structure. Gate drive lines are distributed across multiple wiring layers (first, second, and third wiring layers) with specific positioning relationships between layers. This spatial distribution in the vertical dimension reduces parasitic capacitance between adjacent gate drive lines while maintaining signal integrity and timing precision.
2Area of stationary object
If gate drive lines are positioned close together, then wiring area is reduced, but parasitic capacitance increases causing accumulation timing differences
Solution Approach 1:
The patent resolves the area-captitance tradeoff by utilizing vertical stacking of wiring layers. Gate drive lines that would be close in the horizontal plane are separated in the vertical dimension across different wiring layers, reducing parasitic capacitance while maintaining compact horizontal footprint.
Solution Approach 2:
The patent applies different wiring layer assignments to different regions of the pixel array. Specific gate drive lines are positioned in specific wiring layers based on their functional requirements and spatial relationships, optimizing the local wiring configuration to minimize parasitic capacitance in critical regions while maintaining overall area efficiency.
Data Source
AI summary
A solid-state image pickup device is provided which can inhibit degradation of image quality which may occur when a global electronic shutter operation is performed. A gate drive line for a first transistor of gate drive lines for pixel transistors is positioned in proximity to a converting unit.