CMOS Image Sensor Gate Voltage Control for Fixed Pattern Noise

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Solution Overview

Problem

CMOS image sensors suffer from column fixed pattern noise due to variations in the final inspection critical dimension (FICD) of the gate electrode during the manufacturing process, which affects the driving current and degrades image signal quality.

Innovation Solution

Incorporating a voltage drop unit for the gate electrode of transistors in the CMOS image sensor to expand the saturation region, thereby reducing the gate voltage and eliminating column fixed pattern noise without additional processing steps.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the gate electrode dimensions are controlled during manufacturing, then transistor performance should be consistent, but variations in FICD still cause driving current variations and column fixed pattern noise

Engineering Contradiction:
Improvegate electrode dimension controlVSAvoidcolumn fixed pattern noise
Core Design Contradiction:
Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

The patent changes the electrical parameter (gate voltage) to compensate for dimensional variations. By applying a reduced gate voltage through the voltage drop unit, transistors with varying gate electrode dimensions are adjusted to operate consistently in the saturation region, eliminating the correlation between dimensional variations and driving current variations that causes column FPN

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The voltage drop unit serves as an intermediary element between the gate electrode and the transistor gate. This intermediary component introduces a controlled voltage drop that compensates for dimensional variations, allowing the transistor to operate in the saturation region regardless of manufacturing tolerances in the gate electrode

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If transistors operate in linear region, then circuit design is simpler, but noise performance is degraded due to lack of saturation region operation

Engineering Contradiction:
Improvecircuit design complexityVSAvoidnoise
Core Design Contradiction:
Device complexityVSObject-generated harmful factors

Solution Approach 1:

The patent changes the gate voltage parameter to force saturation region operation. By reducing the gate voltage through the voltage drop unit, the transistor is biased to operate in the saturation region where noise performance is superior, while maintaining relatively simple circuit design without requiring additional active control elements

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9899437B2CMOS image sensor
Publication Date: 2018.02.20 INTELLECTUAL VENTURES II LLC
  • US9899437B2 patent drawing
  • US9899437B2 patent drawing
  • US9899437B2 patent drawing

AI summary

A CMOS image sensor includes a photodiode, a plurality of transistors for transferring charges accumulated at the photodiode to one column line, and a voltage dropping element connected to a gate electrode of at least one transistor among the plurality of transistors for expanding a saturation region of the transistor by dropping down a gate voltage inputted to the gate electrode of the at least one transistor.