CMOS Image Sensor Lateral Graded-Doping Profile Pinned Photodiode
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed CMOS image sensors face challenges with low charge transport efficiency due to weak lateral electric fields in large area photodiodes, image lag, and limited full well capacity, which affect image quality and dynamic range.
Innovation Solution
A CMOS image sensor fabrication method involving a substrate with specific implanting regions and a lateral graded-doping profile pinned photodiode structure, including a transfer transistor, floating diffusion region, and shallow trench isolation, to enhance charge collection and transport efficiency and reduce image lag.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a large area photodiode is used to enhance sensitivity in high-speed CMOS image sensors, then the sensitivity is improved, but the lateral electric field becomes weak causing low charge transport efficiency
Solution Approach 1:
The patent applies local quality by creating a non-uniform doping distribution within the photodiode region. Specifically, a first doped region with higher doping concentration is formed adjacent to the transfer transistor channel, while other regions maintain lower doping concentrations. This localized high-doping area generates a stronger lateral electric field precisely where charge transport is needed, without requiring an overall increase in photodiode doping that would reduce sensitivity.
Solution Approach 2:
The patent changes the doping concentration parameter spatially within the photodiode structure. By implanting dopants at different concentrations in different regions (higher concentration in the first doped region, lower in others), the electric field distribution is modified. This parameter change enables the photodiode to maintain both high sensitivity (through appropriate overall doping) and high charge transport efficiency (through localized high-doping regions creating strong lateral fields).
2Speed
If the exposure time is shortened for high-speed imaging, then the frame rate is improved, but the signal collection capability deteriorates requiring larger photodiode area
Solution Approach 1:
The patent uses local quality enhancement by concentrating dopants in specific high-value regions rather than uniformly throughout the photodiode. The first doped region with higher doping concentration is strategically positioned to maximize charge collection efficiency during short exposure times, enabling high frame rates without sacrificing signal collection capability.
3Quantity of substance
If the full well capacity is increased to enhance dynamic range, then the dynamic range is improved, but the device structure becomes more complex
Solution Approach 1:
The patent achieves increased full well capacity through parameter changes in the doping profile rather than structural modifications. By optimizing the doping concentration distribution (higher in the first doped region, lower in others), the patent enlarges the charge storage capacity and improves dynamic range while maintaining the existing photodiode and transistor structure, thus avoiding increased device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method increases full well capacity, charge transport efficiency, and dynamic range, while minimizing image lag by optimizing the doping profiles and electrical connections within the pixel unit.
Implementation Method 1
forming a first implanting region in the substrate in the first region using a first mask; forming a second implanting region in the first implanting region
Implementation Method 2
The large area PD causes the lateral electric field of the PD region to be weak
Implementation Method 3
the charges of the signal can only be transported by the diffusion of carriers
Data Source
AI summary
The present disclosure provides CMOS image sensors. A CMOS image sensor includes a substrate having a first region and a second region connecting with the first region at a first end of the first region; a transfer transistor formed on the surface of the substrate in the second region; a floating diffusion (FD) region formed in the surface of the substrate at one side of the transfer transistor in the second region; a third implanting region formed in the surface of the substrate 200 in the first region, being formed from a first implanting region; a second implanting region and an adjacent fifth implanting region formed under the third implanting region; and a fourth implanting region formed under the second implanting region and the fifth implanting region, being electrically connected with the third implanting region by the fifth implanting region.