CMOS Image Sensor Substrate Etching via Transparent Hard Mask
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in manufacturing CMOS image sensors lies in forming a thick and uniform photo-resist layer for etching thick substrates, which is difficult due to poor uniformity and the adherence of polymer containing metal, leading to decreased yield.
Innovation Solution
A transparent hard mask layer is formed on the substrate, providing etch selectivity and allowing for a wet process to remove the etch mask layer and adhered polymer, thereby simplifying the etching process and enhancing yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If a thick photo-resist layer is formed for etching thick substrates, then the etching capability is improved, but the uniformity of the photo-resist layer deteriorates
Solution Approach 1:
The patent divides the single thick photo-resist layer into multiple thinner photo-resist layers formed sequentially. Each layer is formed within the optimal thickness range for uniformity, and the layers are combined to achieve the total thickness needed for etching through the thick substrate. This segmentation resolves the contradiction by maintaining good uniformity in each layer while achieving the required total thickness for effective etching.
2Length of stationary object
If a thick photo-resist layer is used for etching, then the etching process is enabled, but polymer containing metal adheres to the photo-resist layer causing yield decrease
Solution Approach 1:
By dividing the thick photo-resist layer into multiple thinner layers, the surface area-to-volume ratio increases, improving access for wet etchants to reach and remove polymer containing metal that adheres during the etching process. This segmentation prevents polymer accumulation from blocking etchant access, thereby maintaining high manufacturing yield while enabling etching of thick substrates.
3Manufacturing precision
If the photo-resist layer thickness is reduced, then the uniformity and ease of formation are improved, but the etching capability through thick substrates deteriorates
Solution Approach 1:
The patent forms multiple thin photo-resist layers sequentially, each with good uniformity, to achieve the cumulative thickness required for etching through thick substrates. This approach maintains the ease of forming uniform thin layers while achieving the total thickness needed for effective etching capability.
Solution Approach 2:
The patent performs preliminary actions by forming multiple thin photo-resist layers in sequence before the etching process. Each layer is carefully formed within the optimal thickness range to ensure uniformity, and the cumulative effect of multiple layers provides sufficient thickness for etching capability through thick substrates.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables easier formation and removal of the etch mask layer, enlarges the process window, and improves the yield of CMOS image sensors by reducing the thickness requirements and addressing uniformity issues.
Implementation Method 1
A transparent hard mask layer is formed on the substrate, providing etch selectivity and allowing for a wet process to remove the etch mask layer and adhered polymer
Data Source
AI summary
A semiconductor device includes a substrate, a conductive layer, a transparent layer, a transparent hard mask layer, a carrier, and a device layer. The substrate has a first surface and a second surface opposite to each other. The conductive layer is disposed on the first surface of the substrate. The transparent layer is disposed on the conductive layer. The transparent hard mask layer is disposed on the transparent layer, in which the substrate has an etch selectivity with respect to the transparent hard mask layer. The device layer is disposed between the carrier and the second surface of the substrate, in which various portions of the device layer are respectively exposed by various through holes which pass through the transparent hard mask layer, the transparent layer, the conductive layer, and the substrate.