CMOS Image Sensor 3D Stacked Pitch Conversion Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
CMOS image sensors face challenges in miniaturization due to larger chip projection areas resulting from conventional stacking techniques, which hinder the use of small-sized lenses and limit camera substrate miniaturization.
Innovation Solution
A multilayer structure is implemented in CMOS image sensors, where the first substrate has a pixel array with specific pitches for column and row level connections, and the second substrate has corresponding pitches for column readout circuits and row drivers, with pitch conversion-use interconnects to reduce the chip projection area by forming slanted interconnects between the end parts of these components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional stacking techniques are used to separate pixel array and peripheral circuits onto different substrates, then integration is improved, but chip projection area increases
Solution Approach 1:
The patent transitions from planar 2D arrangement to 3D stacked arrangement by connecting pixel array substrate and peripheral circuit substrate through TSVs in the vertical dimension, enabling spatial separation while maintaining compact footprint
Solution Approach 2:
The patent nests the peripheral circuit substrate within the projection area of the pixel array substrate by using slanted interconnects that allow the readout circuit substrate to be positioned underneath the pixel array substrate, achieving nested configuration
2Area of stationary object
If chip projection area is reduced to match pixel array size, then camera miniaturization is enabled, but interconnect routing becomes more difficult
Solution Approach 1:
The patent introduces slanted interconnects that extend in the vertical dimension between substrates, providing additional routing space and pathways that avoid conflicts in the horizontal plane, thus enabling compact projection area while maintaining manufacturability
Solution Approach 2:
The patent introduces a lens holder as an intermediary component that supports the lens and positioning structures, serving as a mechanical mediator that facilitates precise alignment and positioning without requiring additional chip area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for the smallest possible chip projection area equal to the pixel array size, enabling further camera miniaturization and application in compact devices like wearable apparatuses without increasing the chip size, while maintaining high-speed signal processing.
Implementation Method 1
a pixel array part (pixel part) having a plurality of pixels performing photoelectric conversion
Data Source
AI summary
A solid-state imaging device comprised of a first substrate on which a pixel part is formed and a second substrate on which a column readout circuit is formed along a column level connection part, a row driver is formed along a row level connection part, and a pitch conversion-use interconnect region including a slanted interconnect for pitch conversion among interconnects is formed, the pitch conversion-use interconnect region is formed at least between the end part of the column readout circuit having a third pitch shorter than the pixel part and the end part of the column level connection part and/or between the end part of the row driver having a fourth pitch shorter than the pixel part and the end part of the row level connection part.